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1* NXP SPI Flash Interface (SPIFI)2 3NXP SPIFI is a specialized SPI interface for serial Flash devices.4It supports one Flash device with 1-, 2- and 4-bits width in SPI5mode 0 or 3. The controller operates in either command or memory6mode. In memory mode the Flash is accessible from the CPU as7normal memory.8 9Required properties:10 - compatible : Should be "nxp,lpc1773-spifi"11 - reg : the first contains the register location and length,12 the second contains the memory mapping address and length13 - reg-names: Should contain the reg names "spifi" and "flash"14 - interrupts : Should contain the interrupt for the device15 - clocks : The clocks needed by the SPIFI controller16 - clock-names : Should contain the clock names "spifi" and "reg"17 18Optional properties:19 - resets : phandle + reset specifier20 21The SPI Flash must be a child of the SPIFI node and must have a22compatible property as specified in bindings/mtd/jedec,spi-nor.txt23 24Optionally it can also contain the following properties.25 - spi-cpol : Controller only supports mode 0 and 3 so either26 both spi-cpol and spi-cpha should be present or27 none of them28 - spi-cpha : See above29 - spi-rx-bus-width : Used to select how many pins that are used30 for input on the controller31 32See bindings/spi/spi-bus.txt for more information.33 34Example:35spifi: spifi@40003000 {36 compatible = "nxp,lpc1773-spifi";37 reg = <0x40003000 0x1000>, <0x14000000 0x4000000>;38 reg-names = "spifi", "flash";39 interrupts = <30>;40 clocks = <&ccu1 CLK_SPIFI>, <&ccu1 CLK_CPU_SPIFI>;41 clock-names = "spifi", "reg";42 resets = <&rgu 53>;43 44 flash@0 {45 compatible = "jedec,spi-nor";46 spi-cpol;47 spi-cpha;48 spi-rx-bus-width = <4>;49 #address-cells = <1>;50 #size-cells = <1>;51 52 partition@0 {53 label = "data";54 reg = <0 0x200000>;55 };56 };57};58 59