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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/mtd/ti,gpmc-nand.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Texas Instruments GPMC NAND Flash controller.8 9maintainers:10 - Tony Lindgren <tony@atomide.com>11 - Roger Quadros <rogerq@kernel.org>12 13description:14 GPMC NAND controller/Flash is represented as a child of the15 GPMC controller node.16 17properties:18 compatible:19 items:20 - enum:21 - ti,am64-nand22 - ti,omap2-nand23 24 reg:25 maxItems: 126 27 interrupts:28 items:29 - description: Interrupt for fifoevent30 - description: Interrupt for termcount31 32 "#address-cells": true33 34 "#size-cells": true35 36 ti,nand-ecc-opt:37 description: Desired ECC algorithm38 $ref: /schemas/types.yaml#/definitions/string39 enum: [sw, ham1, bch4, bch8, bch16]40 41 ti,nand-xfer-type:42 description: Data transfer method between controller and chip.43 $ref: /schemas/types.yaml#/definitions/string44 enum: [prefetch-polled, polled, prefetch-dma, prefetch-irq]45 default: prefetch-polled46 47 ti,elm-id:48 description:49 phandle to the ELM (Error Location Module).50 $ref: /schemas/types.yaml#/definitions/phandle51 52 nand-bus-width:53 description:54 Bus width to the NAND chip55 $ref: /schemas/types.yaml#/definitions/uint3256 enum: [8, 16]57 default: 858 59 rb-gpios:60 description:61 GPIO connection to R/B signal from NAND chip62 maxItems: 163 64allOf:65 - $ref: /schemas/memory-controllers/ti,gpmc-child.yaml66 - $ref: mtd.yaml#67 68required:69 - compatible70 - reg71 - ti,nand-ecc-opt72 73unevaluatedProperties: false74 75examples:76 - |77 #include <dt-bindings/interrupt-controller/arm-gic.h>78 #include <dt-bindings/gpio/gpio.h>79 80 gpmc: memory-controller@50000000 {81 compatible = "ti,am3352-gpmc";82 dmas = <&edma 52 0>;83 dma-names = "rxtx";84 clocks = <&l3s_gclk>;85 clock-names = "fck";86 reg = <0x50000000 0x2000>;87 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;88 gpmc,num-cs = <7>;89 gpmc,num-waitpins = <2>;90 #address-cells = <2>;91 #size-cells = <1>;92 interrupt-controller;93 #interrupt-cells = <2>;94 gpio-controller;95 #gpio-cells = <2>;96 97 ranges = <0 0 0x08000000 0x01000000>; /* CS0 space. Min partition = 16MB */98 nand@0,0 {99 compatible = "ti,omap2-nand";100 reg = <0 0 4>; /* device IO registers */101 interrupt-parent = <&gpmc>;102 interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */103 <1 IRQ_TYPE_NONE>; /* termcount */104 ti,nand-xfer-type = "prefetch-dma";105 ti,nand-ecc-opt = "bch16";106 ti,elm-id = <&elm>;107 #address-cells = <1>;108 #size-cells = <1>;109 110 /* NAND generic properties */111 nand-bus-width = <8>;112 rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */113 114 /* GPMC properties*/115 gpmc,device-width = <1>;116 117 partition@0 {118 label = "NAND.SPL";119 reg = <0x00000000 0x00040000>;120 };121 partition@1 {122 label = "NAND.SPL.backup1";123 reg = <0x00040000 0x00040000>;124 };125 };126 };127