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1* AMD 10GbE driver (amd-xgbe)2 3Required properties:4- compatible: Should be "amd,xgbe-seattle-v1a"5- reg: Address and length of the register sets for the device6 - MAC registers7 - PCS registers8 - SerDes Rx/Tx registers9 - SerDes integration registers (1/2)10 - SerDes integration registers (2/2)11- interrupts: Should contain the amd-xgbe interrupt(s). The first interrupt12 listed is required and is the general device interrupt. If the optional13 amd,per-channel-interrupt property is specified, then one additional14 interrupt for each DMA channel supported by the device should be specified.15 The last interrupt listed should be the PCS auto-negotiation interrupt.16- clocks:17 - DMA clock for the amd-xgbe device (used for calculating the18 correct Rx interrupt watchdog timer value on a DMA channel19 for coalescing)20 - PTP clock for the amd-xgbe device21- clock-names: Should be the names of the clocks22 - "dma_clk" for the DMA clock23 - "ptp_clk" for the PTP clock24- phy-mode: See ethernet.txt file in the same directory25 26Optional properties:27- dma-coherent: Present if dma operations are coherent28- amd,per-channel-interrupt: Indicates that Rx and Tx complete will generate29 a unique interrupt for each DMA channel - this requires an additional30 interrupt be configured for each DMA channel31- amd,speed-set: Speed capabilities of the device32 0 - 1GbE and 10GbE (default)33 1 - 2.5GbE and 10GbE34 35The MAC address will be determined using the optional properties defined in36ethernet.txt.37 38The following optional properties are represented by an array with each39value corresponding to a particular speed. The first array value represents40the setting for the 1GbE speed, the second value for the 2.5GbE speed and41the third value for the 10GbE speed. All three values are required if the42property is used.43- amd,serdes-blwc: Baseline wandering correction enablement44 0 - Off45 1 - On46- amd,serdes-cdr-rate: CDR rate speed selection47- amd,serdes-pq-skew: PQ (data sampling) skew48- amd,serdes-tx-amp: TX amplitude boost49- amd,serdes-dfe-tap-config: DFE taps available to run50- amd,serdes-dfe-tap-enable: DFE taps to enable51 52Example:53 xgbe@e0700000 {54 compatible = "amd,xgbe-seattle-v1a";55 reg = <0 0xe0700000 0 0x80000>,56 <0 0xe0780000 0 0x80000>,57 <0 0xe1240800 0 0x00400>,58 <0 0xe1250000 0 0x00060>,59 <0 0xe1250080 0 0x00004>;60 interrupt-parent = <&gic>;61 interrupts = <0 325 4>,62 <0 326 1>, <0 327 1>, <0 328 1>, <0 329 1>,63 <0 323 4>;64 amd,per-channel-interrupt;65 clocks = <&xgbe_dma_clk>, <&xgbe_ptp_clk>;66 clock-names = "dma_clk", "ptp_clk";67 phy-mode = "xgmii";68 mac-address = [ 02 a1 a2 a3 a4 a5 ];69 amd,speed-set = <0>;70 amd,serdes-blwc = <1>, <1>, <0>;71 amd,serdes-cdr-rate = <2>, <2>, <7>;72 amd,serdes-pq-skew = <10>, <10>, <30>;73 amd,serdes-tx-amp = <15>, <15>, <10>;74 amd,serdes-dfe-tap-config = <3>, <3>, <1>;75 amd,serdes-dfe-tap-enable = <0>, <0>, <127>;76 };77