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1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)2# Copyright 2019 BayLibre, SAS3%YAML 1.24---5$id: http://devicetree.org/schemas/net/amlogic,meson-dwmac.yaml#6$schema: http://devicetree.org/meta-schemas/core.yaml#7 8title: Amlogic Meson DWMAC Ethernet controller9 10maintainers:11 - Neil Armstrong <neil.armstrong@linaro.org>12 - Martin Blumenstingl <martin.blumenstingl@googlemail.com>13 14# We need a select here so we don't match all nodes with 'snps,dwmac'15select:16 properties:17 compatible:18 contains:19 enum:20 - amlogic,meson6-dwmac21 - amlogic,meson8b-dwmac22 - amlogic,meson8m2-dwmac23 - amlogic,meson-gxbb-dwmac24 - amlogic,meson-axg-dwmac25 - amlogic,meson-g12a-dwmac26 required:27 - compatible28 29allOf:30 - $ref: snps,dwmac.yaml#31 - if:32 properties:33 compatible:34 contains:35 enum:36 - amlogic,meson8b-dwmac37 - amlogic,meson8m2-dwmac38 - amlogic,meson-gxbb-dwmac39 - amlogic,meson-axg-dwmac40 - amlogic,meson-g12a-dwmac41 42 then:43 properties:44 clocks:45 minItems: 346 items:47 - description: GMAC main clock48 - description: First parent clock of the internal mux49 - description: Second parent clock of the internal mux50 - description: The clock which drives the timing adjustment logic51 52 clock-names:53 minItems: 354 items:55 - const: stmmaceth56 - const: clkin057 - const: clkin158 - const: timing-adjustment59 60 amlogic,tx-delay-ns:61 enum: [0, 2, 4, 6]62 default: 263 description:64 The internal RGMII TX clock delay (provided by this driver)65 in nanoseconds. When phy-mode is set to "rgmii" then the TX66 delay should be explicitly configured. When the phy-mode is67 set to either "rgmii-id" or "rgmii-txid" the TX clock delay68 is already provided by the PHY. In that case this property69 should be set to 0ns (which disables the TX clock delay in70 the MAC to prevent the clock from going off because both71 PHY and MAC are adding a delay). Any configuration is72 ignored when the phy-mode is set to "rmii".73 74 amlogic,rx-delay-ns:75 deprecated: true76 enum:77 - 078 - 279 default: 080 description:81 The internal RGMII RX clock delay in nanoseconds. Deprecated, use82 rx-internal-delay-ps instead.83 84 rx-internal-delay-ps:85 default: 086 87 - if:88 properties:89 compatible:90 contains:91 enum:92 - amlogic,meson8b-dwmac93 - amlogic,meson8m2-dwmac94 - amlogic,meson-gxbb-dwmac95 - amlogic,meson-axg-dwmac96 then:97 properties:98 rx-internal-delay-ps:99 enum:100 - 0101 - 2000102 103 - if:104 properties:105 compatible:106 contains:107 enum:108 - amlogic,meson-g12a-dwmac109 then:110 properties:111 rx-internal-delay-ps:112 enum:113 - 0114 - 200115 - 400116 - 600117 - 800118 - 1000119 - 1200120 - 1400121 - 1600122 - 1800123 - 2000124 - 2200125 - 2400126 - 2600127 - 2800128 - 3000129 130properties:131 compatible:132 additionalItems: true133 maxItems: 3134 items:135 - enum:136 - amlogic,meson6-dwmac137 - amlogic,meson8b-dwmac138 - amlogic,meson8m2-dwmac139 - amlogic,meson-gxbb-dwmac140 - amlogic,meson-axg-dwmac141 - amlogic,meson-g12a-dwmac142 contains:143 enum:144 - snps,dwmac-3.70a145 - snps,dwmac146 147 reg:148 items:149 - description:150 The first register range should be the one of the DWMAC controller151 - description:152 The second range is is for the Amlogic specific configuration153 (for example the PRG_ETHERNET register range on Meson8b and newer)154 155required:156 - compatible157 - reg158 - interrupts159 - interrupt-names160 - clocks161 - clock-names162 - phy-mode163 164unevaluatedProperties: false165 166examples:167 - |168 ethmac: ethernet@c9410000 {169 compatible = "amlogic,meson-gxbb-dwmac", "snps,dwmac";170 reg = <0xc9410000 0x10000>, <0xc8834540 0x8>;171 interrupts = <8>;172 interrupt-names = "macirq";173 clocks = <&clk_eth>, <&clk_fclk_div2>, <&clk_mpll2>, <&clk_fclk_div2>;174 clock-names = "stmmaceth", "clkin0", "clkin1", "timing-adjustment";175 phy-mode = "rgmii";176 };177