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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/net/cortina,gemini-ethernet.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Cortina Systems Gemini Ethernet Controller8 9maintainers:10 - Linus Walleij <linus.walleij@linaro.org>11 12description: |13 This ethernet controller is found in the Gemini SoC family:14 StorLink SL3512 and SL3516, also known as Cortina Systems15 CS3512 and CS3516.16 17properties:18 compatible:19 const: cortina,gemini-ethernet20 21 reg:22 minItems: 323 description: must contain the global registers and the V-bit and A-bit24 memory areas, in total three register sets.25 26 "#address-cells":27 const: 128 29 "#size-cells":30 const: 131 32 ranges: true33 34# The subnodes represents the two ethernet ports in this device.35# They are not independent of each other since they share resources36# in the parent node, and are thus children.37patternProperties:38 "^ethernet-port@[0-9]+$":39 type: object40 unevaluatedProperties: false41 description: contains the resources for ethernet port42 allOf:43 - $ref: ethernet-controller.yaml#44 properties:45 compatible:46 const: cortina,gemini-ethernet-port47 48 reg:49 items:50 - description: DMA/TOE memory51 - description: GMAC memory area of the port52 53 interrupts:54 maxItems: 155 description: should contain the interrupt line of the port.56 this is nominally a level interrupt active high.57 58 resets:59 maxItems: 160 description: this must provide an SoC-integrated reset line for the port.61 62 clocks:63 maxItems: 164 description: this should contain a handle to the PCLK clock for65 clocking the silicon in this port66 67 clock-names:68 const: PCLK69 70 required:71 - reg72 - compatible73 - interrupts74 - resets75 - clocks76 - clock-names77 78required:79 - compatible80 - reg81 - ranges82 83additionalProperties: false84 85examples:86 - |87 #include <dt-bindings/interrupt-controller/irq.h>88 #include <dt-bindings/clock/cortina,gemini-clock.h>89 #include <dt-bindings/reset/cortina,gemini-reset.h>90 mdio0: mdio {91 #address-cells = <1>;92 #size-cells = <0>;93 phy0: ethernet-phy@1 {94 reg = <1>;95 device_type = "ethernet-phy";96 };97 phy1: ethernet-phy@3 {98 reg = <3>;99 device_type = "ethernet-phy";100 };101 };102 103 104 ethernet@60000000 {105 compatible = "cortina,gemini-ethernet";106 reg = <0x60000000 0x4000>, /* Global registers, queue */107 <0x60004000 0x2000>, /* V-bit */108 <0x60006000 0x2000>; /* A-bit */109 #address-cells = <1>;110 #size-cells = <1>;111 ranges;112 113 gmac0: ethernet-port@0 {114 compatible = "cortina,gemini-ethernet-port";115 reg = <0x60008000 0x2000>, /* Port 0 DMA/TOE */116 <0x6000a000 0x2000>; /* Port 0 GMAC */117 interrupt-parent = <&intcon>;118 interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;119 resets = <&syscon GEMINI_RESET_GMAC0>;120 clocks = <&syscon GEMINI_CLK_GATE_GMAC0>;121 clock-names = "PCLK";122 phy-mode = "rgmii";123 phy-handle = <&phy0>;124 };125 126 gmac1: ethernet-port@1 {127 compatible = "cortina,gemini-ethernet-port";128 reg = <0x6000c000 0x2000>, /* Port 1 DMA/TOE */129 <0x6000e000 0x2000>; /* Port 1 GMAC */130 interrupt-parent = <&intcon>;131 interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;132 resets = <&syscon GEMINI_RESET_GMAC1>;133 clocks = <&syscon GEMINI_CLK_GATE_GMAC1>;134 clock-names = "PCLK";135 phy-mode = "rgmii";136 phy-handle = <&phy1>;137 };138 };139