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1# SPDX-License-Identifier: GPL-2.0-only2%YAML 1.23---4$id: http://devicetree.org/schemas/net/dsa/microchip,ksz.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Microchip KSZ Series Ethernet switches8 9maintainers:10 - Marek Vasut <marex@denx.de>11 - Woojung Huh <Woojung.Huh@microchip.com>12 13allOf:14 - $ref: /schemas/spi/spi-peripheral-props.yaml#15 16properties:17 # See Documentation/devicetree/bindings/net/dsa/dsa.yaml for a list of additional18 # required and optional properties.19 compatible:20 enum:21 - microchip,ksz876522 - microchip,ksz879423 - microchip,ksz879524 - microchip,ksz886325 - microchip,ksz8864 # 4-port version of KSZ8895 family switch26 - microchip,ksz887327 - microchip,ksz8895 # 5-port version of KSZ8895 family switch28 - microchip,ksz947729 - microchip,ksz989730 - microchip,ksz989631 - microchip,ksz956732 - microchip,ksz856533 - microchip,ksz989334 - microchip,ksz956335 - microchip,ksz856336 - microchip,ksz856737 38 reset-gpios:39 description:40 Should be a gpio specifier for a reset line.41 maxItems: 142 43 wakeup-source: true44 45 microchip,synclko-125:46 $ref: /schemas/types.yaml#/definitions/flag47 description:48 Set if the output SYNCLKO frequency should be set to 125MHz instead of 25MHz.49 50 microchip,synclko-disable:51 $ref: /schemas/types.yaml#/definitions/flag52 description:53 Set if the output SYNCLKO clock should be disabled. Do not mix with54 microchip,synclko-125.55 56 microchip,pme-active-high:57 $ref: /schemas/types.yaml#/definitions/flag58 description:59 Indicates if the PME pin polarity is active-high.60 61 microchip,io-drive-strength-microamp:62 description:63 IO Pad Drive Strength64 enum: [8000, 16000]65 default: 1600066 67 microchip,hi-drive-strength-microamp:68 description:69 High Speed Drive Strength. Controls drive strength of GMII / RGMII /70 MII / RMII (except TX_CLK/REFCLKI, COL and CRS) and CLKO_25_125 lines.71 enum: [2000, 4000, 8000, 12000, 16000, 20000, 24000, 28000]72 default: 2400073 74 microchip,lo-drive-strength-microamp:75 description:76 Low Speed Drive Strength. Controls drive strength of TX_CLK / REFCLKI,77 COL, CRS, LEDs, PME_N, NTRP_N, SDO and SDI/SDA/MDIO lines.78 enum: [2000, 4000, 8000, 12000, 16000, 20000, 24000, 28000]79 default: 800080 81 interrupts:82 maxItems: 183 84required:85 - compatible86 - reg87 88if:89 not:90 properties:91 compatible:92 enum:93 - microchip,ksz886394 - microchip,ksz887395then:96 $ref: dsa.yaml#/$defs/ethernet-ports97else:98 patternProperties:99 "^(ethernet-)?ports$":100 patternProperties:101 "^(ethernet-)?port@[0-2]$":102 $ref: dsa-port.yaml#103 unevaluatedProperties: false104 properties:105 microchip,rmii-clk-internal:106 $ref: /schemas/types.yaml#/definitions/flag107 description:108 When ksz88x3 is acting as clock provier (via REFCLKO) it109 can select between internal and external RMII reference110 clock. Internal reference clock means that the clock for111 the RMII of ksz88x3 is provided by the ksz88x3 internally112 and the REFCLKI pin is unconnected. For the external113 reference clock, the clock needs to be fed back to ksz88x3114 via REFCLKI.115 If microchip,rmii-clk-internal is set, ksz88x3 will provide116 rmii reference clock internally, otherwise reference clock117 should be provided externally.118 dependencies:119 microchip,rmii-clk-internal: [ethernet]120 121unevaluatedProperties: false122 123examples:124 - |125 #include <dt-bindings/gpio/gpio.h>126 127 // Ethernet switch connected via SPI to the host, CPU port wired to eth0:128 eth0 {129 fixed-link {130 speed = <1000>;131 full-duplex;132 };133 };134 135 spi {136 #address-cells = <1>;137 #size-cells = <0>;138 139 pinctrl-0 = <&pinctrl_spi_ksz>;140 cs-gpios = <&pioC 25 0>;141 id = <1>;142 143 ksz9477: switch@0 {144 compatible = "microchip,ksz9477";145 reg = <0>;146 reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;147 148 spi-max-frequency = <44000000>;149 150 ethernet-ports {151 #address-cells = <1>;152 #size-cells = <0>;153 port@0 {154 reg = <0>;155 label = "lan1";156 };157 port@1 {158 reg = <1>;159 label = "lan2";160 };161 port@2 {162 reg = <2>;163 label = "lan3";164 };165 port@3 {166 reg = <3>;167 label = "lan4";168 };169 port@4 {170 reg = <4>;171 label = "lan5";172 };173 port@5 {174 reg = <5>;175 ethernet = <ð0>;176 phy-mode = "rgmii";177 178 fixed-link {179 speed = <1000>;180 full-duplex;181 };182 };183 };184 };185 186 ksz8565: switch@1 {187 compatible = "microchip,ksz8565";188 reg = <1>;189 190 spi-max-frequency = <44000000>;191 192 ethernet-ports {193 #address-cells = <1>;194 #size-cells = <0>;195 port@0 {196 reg = <0>;197 label = "lan1";198 };199 port@1 {200 reg = <1>;201 label = "lan2";202 };203 port@2 {204 reg = <2>;205 label = "lan3";206 };207 port@3 {208 reg = <3>;209 label = "lan4";210 };211 port@6 {212 reg = <6>;213 ethernet = <ð0>;214 phy-mode = "rgmii";215 216 fixed-link {217 speed = <1000>;218 full-duplex;219 };220 };221 };222 };223 };224...225