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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/net/dsa/nxp,sja1105.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: NXP SJA1105 Automotive Ethernet Switch Family8 9description:10 The SJA1105 SPI interface requires a CS-to-CLK time (t2 in UM10944.pdf) of at11 least one half of t_CLK. At an SPI frequency of 1MHz, this means a minimum12 cs_sck_delay of 500ns. Ensuring that this SPI timing requirement is observed13 depends on the SPI bus master driver.14 15maintainers:16 - Vladimir Oltean <vladimir.oltean@nxp.com>17 18properties:19 compatible:20 enum:21 - nxp,sja1105e22 - nxp,sja1105t23 - nxp,sja1105p24 - nxp,sja1105q25 - nxp,sja1105r26 - nxp,sja1105s27 - nxp,sja1110a28 - nxp,sja1110b29 - nxp,sja1110c30 - nxp,sja1110d31 32 reg:33 maxItems: 134 35 spi-cpha: true36 spi-cpol: true37 38 # Optional container node for the 2 internal MDIO buses of the SJA111039 # (one for the internal 100base-T1 PHYs and the other for the single40 # 100base-TX PHY). The "reg" property does not have physical significance.41 # The PHY addresses to port correspondence is as follows: for 100base-T1,42 # port 5 has PHY 1, port 6 has PHY 2 etc, while for 100base-TX, port 1 has43 # PHY 1.44 mdios:45 type: object46 additionalProperties: false47 48 properties:49 '#address-cells':50 const: 151 '#size-cells':52 const: 053 54 patternProperties:55 "^mdio@[0-1]$":56 $ref: /schemas/net/mdio.yaml#57 unevaluatedProperties: false58 59 properties:60 compatible:61 oneOf:62 - enum:63 - nxp,sja1110-base-t1-mdio64 - nxp,sja1110-base-tx-mdio65 66 reg:67 oneOf:68 - enum:69 - 070 - 171 72 required:73 - compatible74 - reg75 76patternProperties:77 "^(ethernet-)?ports$":78 additionalProperties: true79 patternProperties:80 "^(ethernet-)?port@[0-9]$":81 allOf:82 - if:83 properties:84 phy-mode:85 contains:86 enum:87 - rgmii88 - rgmii-rxid89 - rgmii-txid90 - rgmii-id91 then:92 properties:93 rx-internal-delay-ps:94 $ref: "#/$defs/internal-delay-ps"95 tx-internal-delay-ps:96 $ref: "#/$defs/internal-delay-ps"97 98required:99 - compatible100 - reg101 102$defs:103 internal-delay-ps:104 description:105 Disable tunable delay lines using 0 ps, or enable them and select106 the phase between 1640 ps (73.8 degree shift at 1Gbps) and 2260 ps107 (101.7 degree shift) in increments of 0.9 degrees (20 ps).108 enum:109 [0, 1640, 1660, 1680, 1700, 1720, 1740, 1760, 1780, 1800, 1820, 1840,110 1860, 1880, 1900, 1920, 1940, 1960, 1980, 2000, 2020, 2040, 2060, 2080,111 2100, 2120, 2140, 2160, 2180, 2200, 2220, 2240, 2260]112 113allOf:114 - $ref: dsa.yaml#/$defs/ethernet-ports115 - $ref: /schemas/spi/spi-peripheral-props.yaml#116 - if:117 properties:118 compatible:119 enum:120 - nxp,sja1105e121 - nxp,sja1105p122 - nxp,sja1105q123 - nxp,sja1105r124 - nxp,sja1105s125 - nxp,sja1105t126 then:127 properties:128 spi-cpol: false129 required:130 - spi-cpha131 else:132 properties:133 spi-cpha: false134 required:135 - spi-cpol136 137unevaluatedProperties: false138 139examples:140 - |141 spi {142 #address-cells = <1>;143 #size-cells = <0>;144 145 ethernet-switch@1 {146 reg = <0x1>;147 compatible = "nxp,sja1105t";148 spi-cpha;149 150 ethernet-ports {151 #address-cells = <1>;152 #size-cells = <0>;153 154 port@0 {155 phy-handle = <&rgmii_phy6>;156 phy-mode = "rgmii-id";157 rx-internal-delay-ps = <0>;158 tx-internal-delay-ps = <0>;159 reg = <0>;160 };161 162 port@1 {163 phy-handle = <&rgmii_phy3>;164 phy-mode = "rgmii-id";165 rx-internal-delay-ps = <0>;166 tx-internal-delay-ps = <0>;167 reg = <1>;168 };169 170 port@2 {171 phy-handle = <&rgmii_phy4>;172 phy-mode = "rgmii-id";173 rx-internal-delay-ps = <0>;174 tx-internal-delay-ps = <0>;175 reg = <2>;176 };177 178 port@3 {179 phy-handle = <&rgmii_phy4>;180 phy-mode = "rgmii-id";181 rx-internal-delay-ps = <0>;182 tx-internal-delay-ps = <0>;183 reg = <3>;184 };185 186 port@4 {187 ethernet = <&enet2>;188 phy-mode = "rgmii";189 rx-internal-delay-ps = <0>;190 tx-internal-delay-ps = <0>;191 reg = <4>;192 193 fixed-link {194 speed = <1000>;195 full-duplex;196 };197 };198 };199 };200 };201