290 lines · yaml
1# SPDX-License-Identifier: GPL-2.02%YAML 1.23---4$id: http://devicetree.org/schemas/net/ethernet-controller.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Ethernet Controller Common Properties8 9maintainers:10 - David S. Miller <davem@davemloft.net>11 12properties:13 $nodename:14 pattern: "^ethernet(@.*)?$"15 16 label:17 description: Human readable label on a port of a box.18 19 local-mac-address:20 description:21 Specifies the MAC address that was assigned to the network device.22 $ref: /schemas/types.yaml#/definitions/uint8-array23 minItems: 624 maxItems: 625 26 mac-address:27 description:28 Specifies the MAC address that was last used by the boot29 program; should be used in cases where the MAC address assigned30 to the device by the boot program is different from the31 local-mac-address property.32 $ref: /schemas/types.yaml#/definitions/uint8-array33 minItems: 634 maxItems: 635 36 max-frame-size:37 $ref: /schemas/types.yaml#/definitions/uint3238 description:39 Maximum transfer unit (IEEE defined MTU), rather than the40 maximum frame size (there\'s contradiction in the Devicetree41 Specification).42 43 max-speed:44 $ref: /schemas/types.yaml#/definitions/uint3245 description:46 Specifies maximum speed in Mbit/s supported by the device.47 48 nvmem-cells:49 maxItems: 150 description:51 Reference to an nvmem node for the MAC address52 53 nvmem-cell-names:54 const: mac-address55 56 phy-connection-type:57 description:58 Specifies interface type between the Ethernet device and a physical59 layer (PHY) device.60 enum:61 # There is not a standard bus between the MAC and the PHY,62 # something proprietary is being used to embed the PHY in the63 # MAC.64 - internal65 - mii66 - gmii67 - sgmii68 - psgmii69 - qsgmii70 - qusgmii71 - tbi72 - rev-mii73 - rmii74 - rev-rmii75 - moca76 77 # RX and TX delays are added by the MAC when required78 - rgmii79 80 # RGMII with internal RX and TX delays provided by the PHY,81 # the MAC should not add the RX or TX delays in this case82 - rgmii-id83 84 # RGMII with internal RX delay provided by the PHY, the MAC85 # should not add an RX delay in this case86 - rgmii-rxid87 88 # RGMII with internal TX delay provided by the PHY, the MAC89 # should not add an TX delay in this case90 - rgmii-txid91 - rtbi92 - smii93 - xgmii94 - trgmii95 - 1000base-x96 - 2500base-x97 - 5gbase-r98 - rxaui99 - xaui100 101 # 10GBASE-KR, XFI, SFI102 - 10gbase-kr103 - usxgmii104 - 10gbase-r105 - 25gbase-r106 - 10g-qxgmii107 108 phy-mode:109 $ref: "#/properties/phy-connection-type"110 111 pcs-handle:112 $ref: /schemas/types.yaml#/definitions/phandle-array113 items:114 maxItems: 1115 description:116 Specifies a reference to a node representing a PCS PHY device on a MDIO117 bus to link with an external PHY (phy-handle) if exists.118 119 pcs-handle-names:120 description:121 The name of each PCS in pcs-handle.122 123 phy-handle:124 $ref: /schemas/types.yaml#/definitions/phandle125 description:126 Specifies a reference to a node representing a PHY device.127 128 phy:129 $ref: "#/properties/phy-handle"130 deprecated: true131 132 phy-device:133 $ref: "#/properties/phy-handle"134 deprecated: true135 136 rx-fifo-depth:137 $ref: /schemas/types.yaml#/definitions/uint32138 description:139 The size of the controller\'s receive fifo in bytes. This is used140 for components that can have configurable receive fifo sizes,141 and is useful for determining certain configuration settings142 such as flow control thresholds.143 144 sfp:145 $ref: /schemas/types.yaml#/definitions/phandle146 description:147 Specifies a reference to a node representing a SFP cage.148 149 tx-fifo-depth:150 $ref: /schemas/types.yaml#/definitions/uint32151 description:152 The size of the controller\'s transmit fifo in bytes. This153 is used for components that can have configurable fifo sizes.154 155 managed:156 description:157 Specifies the PHY management type. If auto is set and fixed-link158 is not specified, it uses MDIO for management.159 $ref: /schemas/types.yaml#/definitions/string160 default: auto161 enum:162 - auto163 - in-band-status164 165 fixed-link:166 oneOf:167 - $ref: /schemas/types.yaml#/definitions/uint32-array168 deprecated: true169 items:170 - minimum: 0171 maximum: 31172 description:173 Emulated PHY ID, choose any but unique to the all174 specified fixed-links175 176 - enum: [0, 1]177 description:178 Duplex configuration. 0 for half duplex or 1 for179 full duplex180 181 - enum: [10, 100, 1000, 2500, 10000]182 description:183 Link speed in Mbits/sec.184 185 - enum: [0, 1]186 description:187 Pause configuration. 0 for no pause, 1 for pause188 189 - enum: [0, 1]190 description:191 Asymmetric pause configuration. 0 for no asymmetric192 pause, 1 for asymmetric pause193 - type: object194 additionalProperties: false195 properties:196 speed:197 description:198 Link speed.199 $ref: /schemas/types.yaml#/definitions/uint32200 enum: [10, 100, 1000, 2500, 10000]201 202 full-duplex:203 $ref: /schemas/types.yaml#/definitions/flag204 description:205 Indicates that full-duplex is used. When absent, half206 duplex is assumed.207 208 pause:209 $ref: /schemas/types.yaml#/definitions/flag210 description:211 Indicates that pause should be enabled.212 213 asym-pause:214 $ref: /schemas/types.yaml#/definitions/flag215 description:216 Indicates that asym_pause should be enabled.217 218 link-gpios:219 maxItems: 1220 description:221 GPIO to determine if the link is up222 223 required:224 - speed225 226 leds:227 description:228 Describes the LEDs associated by Ethernet Controller.229 These LEDs are not integrated in the PHY and PHY doesn't have any230 control on them. Ethernet Controller regs are used to control231 these defined LEDs.232 233 type: object234 235 properties:236 '#address-cells':237 const: 1238 239 '#size-cells':240 const: 0241 242 patternProperties:243 '^led@[a-f0-9]+$':244 $ref: /schemas/leds/common.yaml#245 246 properties:247 reg:248 maxItems: 1249 description:250 This define the LED index in the PHY or the MAC. It's really251 driver dependent and required for ports that define multiple252 LED for the same port.253 254 required:255 - reg256 257 unevaluatedProperties: false258 259 additionalProperties: false260 261dependencies:262 pcs-handle-names: [pcs-handle]263 264allOf:265 - if:266 properties:267 phy-mode:268 contains:269 enum:270 - rgmii271 - rgmii-rxid272 - rgmii-txid273 - rgmii-id274 then:275 properties:276 rx-internal-delay-ps:277 description:278 RGMII Receive Clock Delay defined in pico seconds. This is used for279 controllers that have configurable RX internal delays. If this280 property is present then the MAC applies the RX delay.281 tx-internal-delay-ps:282 description:283 RGMII Transmit Clock Delay defined in pico seconds. This is used for284 controllers that have configurable TX internal delays. If this285 property is present then the MAC applies the TX delay.286 287additionalProperties: true288 289...290