271 lines · yaml
1# SPDX-License-Identifier: GPL-2.02%YAML 1.23---4$id: http://devicetree.org/schemas/net/fsl,fec.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Freescale Fast Ethernet Controller (FEC)8 9maintainers:10 - Shawn Guo <shawnguo@kernel.org>11 - Wei Fang <wei.fang@nxp.com>12 - NXP Linux Team <linux-imx@nxp.com>13 14allOf:15 - $ref: ethernet-controller.yaml#16 17properties:18 compatible:19 oneOf:20 - enum:21 - fsl,imx25-fec22 - fsl,imx27-fec23 - fsl,imx28-fec24 - fsl,imx6q-fec25 - fsl,mvf600-fec26 - fsl,s32v234-fec27 - items:28 - enum:29 - fsl,imx53-fec30 - fsl,imx6sl-fec31 - const: fsl,imx25-fec32 - items:33 - enum:34 - fsl,imx35-fec35 - fsl,imx51-fec36 - const: fsl,imx27-fec37 - items:38 - enum:39 - fsl,imx6ul-fec40 - fsl,imx6sx-fec41 - const: fsl,imx6q-fec42 - items:43 - enum:44 - fsl,imx7d-fec45 - const: fsl,imx6sx-fec46 - items:47 - const: fsl,imx8mq-fec48 - const: fsl,imx6sx-fec49 - items:50 - enum:51 - fsl,imx8mm-fec52 - fsl,imx8mn-fec53 - fsl,imx8mp-fec54 - fsl,imx93-fec55 - const: fsl,imx8mq-fec56 - const: fsl,imx6sx-fec57 - items:58 - const: fsl,imx8qm-fec59 - const: fsl,imx6sx-fec60 - items:61 - enum:62 - fsl,imx8dxl-fec63 - fsl,imx8qxp-fec64 - const: fsl,imx8qm-fec65 - const: fsl,imx6sx-fec66 - items:67 - enum:68 - fsl,imx8ulp-fec69 - const: fsl,imx6ul-fec70 - const: fsl,imx6q-fec71 72 reg:73 maxItems: 174 75 interrupts:76 minItems: 177 maxItems: 478 79 interrupt-names:80 oneOf:81 - items:82 - const: int083 - items:84 - const: int085 - const: pps86 - items:87 - const: int088 - const: int189 - const: int290 - items:91 - const: int092 - const: int193 - const: int294 - const: pps95 96 clocks:97 minItems: 298 maxItems: 599 description:100 The "ipg", for MAC ipg_clk_s, ipg_clk_mac_s that are for register accessing.101 The "ahb", for MAC ipg_clk, ipg_clk_mac that are bus clock.102 The "ptp"(option), for IEEE1588 timer clock that requires the clock.103 The "enet_clk_ref"(option), for MAC transmit/receiver reference clock like104 RGMII TXC clock or RMII reference clock. It depends on board design,105 the clock is required if RGMII TXC and RMII reference clock source from106 SOC internal PLL.107 The "enet_out"(option), output clock for external device, like supply clock108 for PHY. The clock is required if PHY clock source from SOC.109 The "enet_2x_txclk"(option), for RGMII sampling clock which fixed at 250Mhz.110 The clock is required if SoC RGMII enable clock delay.111 112 clock-names:113 minItems: 2114 maxItems: 5115 items:116 enum:117 - ipg118 - ahb119 - ptp120 - enet_clk_ref121 - enet_out122 - enet_2x_txclk123 124 phy-mode: true125 126 phy-handle: true127 128 fixed-link: true129 130 local-mac-address: true131 132 mac-address: true133 134 nvmem-cells: true135 136 nvmem-cell-names: true137 138 tx-internal-delay-ps:139 enum: [0, 2000]140 141 rx-internal-delay-ps:142 enum: [0, 2000]143 144 phy-supply:145 description:146 Regulator that powers the Ethernet PHY.147 148 power-domains:149 maxItems: 1150 151 fsl,num-tx-queues:152 $ref: /schemas/types.yaml#/definitions/uint32153 description:154 The property is valid for enet-avb IP, which supports hw multi queues.155 Should specify the tx queue number, otherwise set tx queue number to 1.156 enum: [1, 2, 3]157 158 fsl,num-rx-queues:159 $ref: /schemas/types.yaml#/definitions/uint32160 description:161 The property is valid for enet-avb IP, which supports hw multi queues.162 Should specify the rx queue number, otherwise set rx queue number to 1.163 enum: [1, 2, 3]164 165 fsl,magic-packet:166 $ref: /schemas/types.yaml#/definitions/flag167 description:168 If present, indicates that the hardware supports waking up via magic packet.169 170 fsl,err006687-workaround-present:171 $ref: /schemas/types.yaml#/definitions/flag172 description:173 If present indicates that the system has the hardware workaround for174 ERR006687 applied and does not need a software workaround.175 176 fsl,stop-mode:177 $ref: /schemas/types.yaml#/definitions/phandle-array178 items:179 - items:180 - description: phandle to general purpose register node181 - description: the gpr register offset for ENET stop request182 - description: the gpr bit offset for ENET stop request183 description:184 Register bits of stop mode control, the format is <&gpr req_gpr req_bit>.185 186 mdio:187 $ref: mdio.yaml#188 unevaluatedProperties: false189 description:190 Specifies the mdio bus in the FEC, used as a container for phy nodes.191 192 # Deprecated optional properties:193 # To avoid these, create a phy node according to ethernet-phy.yaml in the same194 # directory, and point the FEC's "phy-handle" property to it. Then use195 # the phy's reset binding, again described by ethernet-phy.yaml.196 197 phy-reset-gpios:198 deprecated: true199 description:200 Should specify the gpio for phy reset.201 202 phy-reset-duration:203 $ref: /schemas/types.yaml#/definitions/uint32204 deprecated: true205 description:206 Reset duration in milliseconds. Should present only if property207 "phy-reset-gpios" is available. Missing the property will have the208 duration be 1 millisecond. Numbers greater than 1000 are invalid209 and 1 millisecond will be used instead.210 211 phy-reset-active-high:212 type: boolean213 deprecated: true214 description:215 If present then the reset sequence using the GPIO specified in the216 "phy-reset-gpios" property is reversed (H=reset state, L=operation state).217 218 phy-reset-post-delay:219 $ref: /schemas/types.yaml#/definitions/uint32220 deprecated: true221 description:222 Post reset delay in milliseconds. If present then a delay of phy-reset-post-delay223 milliseconds will be observed after the phy-reset-gpios has been toggled.224 Can be omitted thus no delay is observed. Delay is in range of 1ms to 1000ms.225 Other delays are invalid.226 227 iommus:228 maxItems: 1229 230required:231 - compatible232 - reg233 - interrupts234 235# FIXME: We had better set additionalProperties to false to avoid invalid or at236# least undocumented properties. However, PHY may have a deprecated option to237# place PHY OF properties in the MAC node, such as Micrel PHY, and we can find238# these boards which is based on i.MX6QDL.239unevaluatedProperties: false240 241examples:242 - |243 ethernet@83fec000 {244 compatible = "fsl,imx51-fec", "fsl,imx27-fec";245 reg = <0x83fec000 0x4000>;246 interrupts = <87>;247 phy-mode = "mii";248 phy-reset-gpios = <&gpio2 14 0>;249 phy-supply = <®_fec_supply>;250 };251 252 ethernet@83fed000 {253 compatible = "fsl,imx51-fec", "fsl,imx27-fec";254 reg = <0x83fed000 0x4000>;255 interrupts = <87>;256 phy-mode = "mii";257 phy-reset-gpios = <&gpio2 14 0>;258 phy-supply = <®_fec_supply>;259 phy-handle = <ðphy0>;260 261 mdio {262 #address-cells = <1>;263 #size-cells = <0>;264 265 ethphy0: ethernet-phy@0 {266 compatible = "ethernet-phy-ieee802.3-c22";267 reg = <0>;268 };269 };270 };271