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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/net/fsl,fman-mdio.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Freescale Frame Manager MDIO Device8 9maintainers:10 - Frank Li <Frank.Li@nxp.com>11 12description: FMan MDIO Node.13 The MDIO is a bus to which the PHY devices are connected.14 15properties:16 compatible:17 enum:18 - fsl,fman-mdio19 - fsl,fman-xmdio20 - fsl,fman-memac-mdio21 description:22 Must include "fsl,fman-mdio" for 1 Gb/s MDIO from FMan v2.23 Must include "fsl,fman-xmdio" for 10 Gb/s MDIO from FMan v2.24 Must include "fsl,fman-memac-mdio" for 1/10 Gb/s MDIO from25 FMan v3.26 27 reg:28 maxItems: 129 30 clocks:31 items:32 - description: A reference to the input clock of the controller33 from which the MDC frequency is derived.34 35 interrupts:36 maxItems: 137 38 fsl,fman-internal-mdio:39 $ref: /schemas/types.yaml#/definitions/flag40 description:41 Fman has internal MDIO for internal PCS(Physical42 Coding Sublayer) PHYs and external MDIO for external PHYs.43 The settings and programming routines for internal/external44 MDIO are different. Must be included for internal MDIO.45 46 fsl,erratum-a009885:47 $ref: /schemas/types.yaml#/definitions/flag48 description: Indicates the presence of the A00988549 erratum describing that the contents of MDIO_DATA may50 become corrupt unless it is read within 16 MDC cycles51 of MDIO_CFG[BSY] being cleared, when performing an52 MDIO read operation.53 54 fsl,erratum-a011043:55 $ref: /schemas/types.yaml#/definitions/flag56 description:57 Indicates the presence of the A011043 erratum58 describing that the MDIO_CFG[MDIO_RD_ER] bit may be falsely59 set when reading internal PCS registers. MDIO reads to60 internal PCS registers may result in having the61 MDIO_CFG[MDIO_RD_ER] bit set, even when there is no error and62 read data (MDIO_DATA[MDIO_DATA]) is correct.63 Software may get false read error when reading internal64 PCS registers through MDIO. As a workaround, all internal65 MDIO accesses should ignore the MDIO_CFG[MDIO_RD_ER] bit.66 67 For internal PHY device on internal mdio bus, a PHY node should be created.68 See the definition of the PHY node in booting-without-of.txt for an69 example of how to define a PHY (Internal PHY has no interrupt line).70 - For "fsl,fman-mdio" compatible internal mdio bus, the PHY is TBI PHY.71 - For "fsl,fman-memac-mdio" compatible internal mdio bus, the PHY is PCS PHY.72 The PCS PHY address should correspond to the value of the appropriate73 MDEV_PORT.74 75 little-endian:76 $ref: /schemas/types.yaml#/definitions/flag77 description:78 IP block is little-endian mode. The default endian mode is big-endian.79 80required:81 - compatible82 - reg83 84allOf:85 - $ref: mdio.yaml#86 87unevaluatedProperties: false88 89examples:90 - |91 mdio@f1000 {92 compatible = "fsl,fman-xmdio";93 reg = <0xf1000 0x1000>;94 interrupts = <101 2 0 0>;95 };96 97 - |98 mdio@e3120 {99 compatible = "fsl,fman-mdio";100 reg = <0xe3120 0xee0>;101 fsl,fman-internal-mdio;102 #address-cells = <1>;103 #size-cells = <0>;104 105 tbi-phy@8 {106 reg = <0x8>;107 device_type = "tbi-phy";108 };109 };110 111 - |112 mdio@f1000 {113 compatible = "fsl,fman-memac-mdio";114 reg = <0xf1000 0x1000>;115 fsl,fman-internal-mdio;116 #address-cells = <1>;117 #size-cells = <0>;118 119 pcsphy6: ethernet-phy@0 {120 reg = <0x0>;121 };122 };123 124