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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/net/fsl,fman.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Freescale Frame Manager Device8 9maintainers:10 - Frank Li <Frank.Li@nxp.com>11 12description:13 Due to the fact that the FMan is an aggregation of sub-engines (ports, MACs,14 etc.) the FMan node will have child nodes for each of them.15 16properties:17 compatible:18 enum:19 - fsl,fman20 description:21 FMan version can be determined via FM_IP_REV_1 register in the22 FMan block. The offset is 0xc4 from the beginning of the23 Frame Processing Manager memory map (0xc3000 from the24 beginning of the FMan node).25 26 cell-index:27 $ref: /schemas/types.yaml#/definitions/uint3228 description: |29 Specifies the index of the FMan unit.30 31 The cell-index value may be used by the SoC, to identify the32 FMan unit in the SoC memory map. In the table below,33 there's a description of the cell-index use in each SoC:34 35 - P1023:36 register[bit] FMan unit cell-index37 ============================================================38 DEVDISR[1] 1 039 40 - P2041, P3041, P4080 P5020, P5040:41 register[bit] FMan unit cell-index42 ============================================================43 DCFG_DEVDISR2[6] 1 044 DCFG_DEVDISR2[14] 2 145 (Second FM available only in P4080 and P5040)46 47 - B4860, T1040, T2080, T4240:48 register[bit] FMan unit cell-index49 ============================================================50 DCFG_CCSR_DEVDISR2[24] 1 051 DCFG_CCSR_DEVDISR2[25] 2 152 (Second FM available only in T4240)53 54 DEVDISR, DCFG_DEVDISR2 and DCFG_CCSR_DEVDISR2 are located in55 the specific SoC "Device Configuration/Pin Control" Memory56 Map.57 58 reg:59 items:60 - description: BMI configuration registers.61 - description: QMI configuration registers.62 - description: DMA configuration registers.63 - description: FPM configuration registers.64 - description: FMan controller configuration registers.65 minItems: 166 67 ranges: true68 69 clocks:70 maxItems: 171 72 clock-names:73 items:74 - const: fmanclk75 76 interrupts:77 items:78 - description: The first element is associated with the event interrupts.79 - description: the second element is associated with the error interrupts.80 81 dma-coherent: true82 83 ptimer-handle:84 $ref: /schemas/types.yaml#/definitions/phandle85 description: see ptp/fsl,ptp.yaml86 87 fsl,qman-channel-range:88 $ref: /schemas/types.yaml#/definitions/uint32-array89 description:90 Specifies the range of the available dedicated91 channels in the FMan. The first cell specifies the beginning92 of the range and the second cell specifies the number of93 channels94 items:95 - description: The first cell specifies the beginning of the range.96 - description: |97 The second cell specifies the number of channels.98 Further information available at:99 "Work Queue (WQ) Channel Assignments in the QMan" section100 in DPAA Reference Manual.101 102 fsl,qman:103 $ref: /schemas/types.yaml#/definitions/phandle104 description: See soc/fsl/qman.txt105 106 fsl,bman:107 $ref: /schemas/types.yaml#/definitions/phandle108 description: See soc/fsl/bman.txt109 110 fsl,erratum-a050385:111 $ref: /schemas/types.yaml#/definitions/flag112 description: A boolean property. Indicates the presence of the113 erratum A050385 which indicates that DMA transactions that are114 split can result in a FMan lock.115 116 '#address-cells':117 const: 1118 119 '#size-cells':120 const: 1121 122patternProperties:123 '^muram@[a-f0-9]+$':124 $ref: fsl,fman-muram.yaml125 126 '^port@[a-f0-9]+$':127 $ref: fsl,fman-port.yaml128 129 '^ethernet@[a-f0-9]+$':130 $ref: fsl,fman-dtsec.yaml131 132 '^mdio@[a-f0-9]+$':133 $ref: fsl,fman-mdio.yaml134 135 '^phc@[a-f0-9]+$':136 $ref: /schemas/ptp/fsl,ptp.yaml137 138required:139 - compatible140 - cell-index141 - reg142 - ranges143 - clocks144 - clock-names145 - interrupts146 - fsl,qman-channel-range147 148additionalProperties: false149 150examples:151 - |152 #include <dt-bindings/interrupt-controller/irq.h>153 154 fman@400000 {155 compatible = "fsl,fman";156 reg = <0x400000 0x100000>;157 ranges = <0 0x400000 0x100000>;158 #address-cells = <1>;159 #size-cells = <1>;160 cell-index = <1>;161 clocks = <&fman_clk>;162 clock-names = "fmanclk";163 interrupts = <96 IRQ_TYPE_EDGE_FALLING>,164 <16 IRQ_TYPE_EDGE_FALLING>;165 fsl,qman-channel-range = <0x40 0xc>;166 167 muram@0 {168 compatible = "fsl,fman-muram";169 reg = <0x0 0x28000>;170 };171 172 port@81000 {173 cell-index = <1>;174 compatible = "fsl,fman-v2-port-oh";175 reg = <0x81000 0x1000>;176 };177 178 fman1_rx_0x8: port@88000 {179 cell-index = <0x8>;180 compatible = "fsl,fman-v2-port-rx";181 reg = <0x88000 0x1000>;182 };183 184 fman1_tx_0x28: port@a8000 {185 cell-index = <0x28>;186 compatible = "fsl,fman-v2-port-tx";187 reg = <0xa8000 0x1000>;188 };189 190 ethernet@e0000 {191 compatible = "fsl,fman-dtsec";192 cell-index = <0>;193 reg = <0xe0000 0x1000>;194 ptp-timer = <&ptp_timer>;195 fsl,fman-ports = <&fman1_rx_0x8 &fman1_tx_0x28>;196 tbi-handle = <&tbi5>;197 };198 199 ptp_timer: phc@fe000 {200 compatible = "fsl,fman-ptp-timer";201 reg = <0xfe000 0x1000>;202 interrupts = <12 IRQ_TYPE_LEVEL_LOW>;203 };204 205 mdio@f1000 {206 compatible = "fsl,fman-xmdio";207 reg = <0xf1000 0x1000>;208 interrupts = <101 IRQ_TYPE_EDGE_FALLING>;209 };210 };211