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1Hisilicon Fast Ethernet MAC controller2 3Required properties:4- compatible: should contain one of the following version strings:5 * "hisilicon,hisi-femac-v1"6 * "hisilicon,hisi-femac-v2"7 and the soc string "hisilicon,hi3516cv300-femac".8- reg: specifies base physical address(s) and size of the device registers.9 The first region is the MAC core register base and size.10 The second region is the global MAC control register.11- interrupts: should contain the MAC interrupt.12- clocks: A phandle to the MAC main clock.13- resets: should contain the phandle to the MAC reset signal(required) and14 the PHY reset signal(optional).15- reset-names: should contain the reset signal name "mac"(required)16 and "phy"(optional).17- phy-mode: see ethernet.txt [1].18- phy-handle: see ethernet.txt [1].19- hisilicon,phy-reset-delays-us: triplet of delays if PHY reset signal given.20 The 1st cell is reset pre-delay in micro seconds.21 The 2nd cell is reset pulse in micro seconds.22 The 3rd cell is reset post-delay in micro seconds.23 24The MAC address will be determined using the optional properties25defined in ethernet.txt[1].26 27[1] Documentation/devicetree/bindings/net/ethernet.txt28 29Example:30 hisi_femac: ethernet@10090000 {31 compatible = "hisilicon,hi3516cv300-femac","hisilicon,hisi-femac-v2";32 reg = <0x10090000 0x1000>,<0x10091300 0x200>;33 interrupts = <12>;34 clocks = <&crg HI3518EV200_ETH_CLK>;35 resets = <&crg 0xec 0>,<&crg 0xec 3>;36 reset-names = "mac","phy";37 mac-address = [00 00 00 00 00 00];38 phy-mode = "mii";39 phy-handle = <&phy0>;40 hisilicon,phy-reset-delays-us = <10000 20000 20000>;41 };42