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1Hisilicon hix5hd2 gmac controller2 3Required properties:4- compatible: should contain one of the following SoC strings:5 * "hisilicon,hix5hd2-gmac"6 * "hisilicon,hi3798cv200-gmac"7 * "hisilicon,hi3516a-gmac"8 and one of the following version string:9 * "hisilicon,hisi-gmac-v1"10 * "hisilicon,hisi-gmac-v2"11 The version v1 includes SoCs hix5hd2.12 The version v2 includes SoCs hi3798cv200, hi3516a.13- reg: specifies base physical address(s) and size of the device registers.14 The first region is the MAC register base and size.15 The second region is external interface control register.16- interrupts: should contain the MAC interrupt.17- #address-cells: must be <1>.18- #size-cells: must be <0>.19- phy-mode: see ethernet.txt [1].20- phy-handle: see ethernet.txt [1].21- clocks: clock phandle and specifier pair.22- clock-names: contain the clock name "mac_core"(required) and "mac_ifc"(optional).23- resets: should contain the phandle to the MAC core reset signal(optional),24 the MAC interface reset signal(optional)25 and the PHY reset signal(optional).26- reset-names: contain the reset signal name "mac_core"(optional),27 "mac_ifc"(optional) and "phy"(optional).28- hisilicon,phy-reset-delays-us: triplet of delays if PHY reset signal given.29 The 1st cell is reset pre-delay in micro seconds.30 The 2nd cell is reset pulse in micro seconds.31 The 3rd cell is reset post-delay in micro seconds.32 33The MAC address will be determined using the properties defined in34ethernet.txt[1].35 36- PHY subnode: inherits from phy binding [2]37 38[1] Documentation/devicetree/bindings/net/ethernet.txt39[2] Documentation/devicetree/bindings/net/phy.txt40 41Example:42 gmac0: ethernet@f9840000 {43 compatible = "hisilicon,hi3798cv200-gmac", "hisilicon,hisi-gmac-v2";44 reg = <0xf9840000 0x1000>,<0xf984300c 0x4>;45 interrupts = <0 71 4>;46 #address-cells = <1>;47 #size-cells = <0>;48 phy-mode = "rgmii";49 phy-handle = <&phy2>;50 mac-address = [00 00 00 00 00 00];51 clocks = <&crg HISTB_ETH0_MAC_CLK>, <&crg HISTB_ETH0_MACIF_CLK>;52 clock-names = "mac_core", "mac_ifc";53 resets = <&crg 0xcc 8>, <&crg 0xcc 10>, <&crg 0xcc 12>;54 reset-names = "mac_core", "mac_ifc", "phy";55 hisilicon,phy-reset-delays-us = <10000 10000 30000>;56 57 phy2: ethernet-phy@2 {58 reg = <2>;59 };60 };61