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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/net/marvell,pp2.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Marvell CN913X / Marvell Armada 375, 7K, 8K Ethernet Controller8 9maintainers:10 - Marcin Wojtas <mw@semihalf.com>11 - Russell King <linux@armlinux.org>12 13description: |14 Marvell Armada 375 Ethernet Controller (PPv2.1)15 Marvell Armada 7K/8K Ethernet Controller (PPv2.2)16 Marvell CN913X Ethernet Controller (PPv2.3)17 18properties:19 compatible:20 enum:21 - marvell,armada-375-pp222 - marvell,armada-7k-pp2223 24 reg:25 minItems: 326 maxItems: 427 28 "#address-cells":29 const: 130 31 "#size-cells":32 const: 033 34 clocks:35 minItems: 236 items:37 - description: main controller clock38 - description: GOP clock39 - description: MG clock40 - description: MG Core clock41 - description: AXI clock42 43 clock-names:44 minItems: 245 items:46 - const: pp_clk47 - const: gop_clk48 - const: mg_clk49 - const: mg_core_clk50 - const: axi_clk51 52 dma-coherent: true53 54 marvell,system-controller:55 $ref: /schemas/types.yaml#/definitions/phandle56 description: a phandle to the system controller.57 58patternProperties:59 '^(ethernet-)?port@[0-2]$':60 type: object61 description: subnode for each ethernet port.62 $ref: ethernet-controller.yaml#63 unevaluatedProperties: false64 65 properties:66 reg:67 description: ID of the port from the MAC point of view.68 maximum: 269 70 interrupts:71 minItems: 172 maxItems: 1073 description: interrupt(s) for the port74 75 interrupt-names:76 minItems: 177 items:78 - const: hif079 - const: hif180 - const: hif281 - const: hif382 - const: hif483 - const: hif584 - const: hif685 - const: hif786 - const: hif887 - const: link88 89 description: >90 if more than a single interrupt for is given, must be the91 name associated to the interrupts listed. Valid names are:92 "hifX", with X in [0..8], and "link". The names "tx-cpu0",93 "tx-cpu1", "tx-cpu2", "tx-cpu3" and "rx-shared" are supported94 for backward compatibility but shouldn't be used for new95 additions.96 97 phys:98 minItems: 199 maxItems: 2100 description: >101 Generic PHY, providing SerDes connectivity. For most modes,102 one lane is sufficient, but some (e.g. RXAUI) may require two.103 104 phy-mode:105 enum:106 - gmii107 - sgmii108 - rgmii-id109 - 1000base-x110 - 2500base-x111 - 5gbase-r112 - rxaui113 - 10gbase-r114 115 port-id:116 $ref: /schemas/types.yaml#/definitions/uint32117 deprecated: true118 description: >119 ID of the port from the MAC point of view.120 Legacy binding for backward compatibility.121 122 marvell,loopback:123 $ref: /schemas/types.yaml#/definitions/flag124 description: port is loopback mode.125 126 gop-port-id:127 $ref: /schemas/types.yaml#/definitions/uint32128 description: >129 only for marvell,armada-7k-pp22, ID of the port from the130 GOP (Group Of Ports) point of view. This ID is used to index the131 per-port registers in the second register area.132 133 required:134 - reg135 - interrupts136 - phy-mode137 - port-id138 139required:140 - compatible141 - reg142 - clocks143 - clock-names144 145allOf:146 - if:147 properties:148 compatible:149 const: marvell,armada-7k-pp22150 then:151 properties:152 reg:153 items:154 - description: Packet Processor registers155 - description: Networking interfaces registers156 - description: CM3 address space used for TX Flow Control157 158 clocks:159 minItems: 5160 161 clock-names:162 minItems: 5163 164 patternProperties:165 '^(ethernet-)?port@[0-2]$':166 required:167 - gop-port-id168 169 required:170 - marvell,system-controller171 else:172 properties:173 reg:174 items:175 - description: Packet Processor registers176 - description: LMS registers177 - description: Register area per eth0178 - description: Register area per eth1179 180 clocks:181 maxItems: 2182 183 clock-names:184 maxItems: 2185 186 patternProperties:187 '^(ethernet-)?port@[0-1]$':188 properties:189 reg:190 maximum: 1191 192 gop-port-id: false193 194additionalProperties: false195 196examples:197 - |198 // For Armada 375 variant199 #include <dt-bindings/interrupt-controller/mvebu-icu.h>200 #include <dt-bindings/interrupt-controller/arm-gic.h>201 202 ethernet@f0000 {203 #address-cells = <1>;204 #size-cells = <0>;205 compatible = "marvell,armada-375-pp2";206 reg = <0xf0000 0xa000>,207 <0xc0000 0x3060>,208 <0xc4000 0x100>,209 <0xc5000 0x100>;210 clocks = <&gateclk 3>, <&gateclk 19>;211 clock-names = "pp_clk", "gop_clk";212 213 ethernet-port@0 {214 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;215 reg = <0>;216 port-id = <0>; /* For backward compatibility. */217 phy = <&phy0>;218 phy-mode = "rgmii-id";219 };220 221 ethernet-port@1 {222 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;223 reg = <1>;224 port-id = <1>; /* For backward compatibility. */225 phy = <&phy3>;226 phy-mode = "gmii";227 };228 };229 230 - |231 // For Armada 7k/8k and Cn913x variants232 #include <dt-bindings/interrupt-controller/mvebu-icu.h>233 #include <dt-bindings/interrupt-controller/arm-gic.h>234 235 ethernet@0 {236 #address-cells = <1>;237 #size-cells = <0>;238 compatible = "marvell,armada-7k-pp22";239 reg = <0x0 0x100000>, <0x129000 0xb000>, <0x220000 0x800>;240 clocks = <&cp0_clk 1 3>, <&cp0_clk 1 9>,241 <&cp0_clk 1 5>, <&cp0_clk 1 6>, <&cp0_clk 1 18>;242 clock-names = "pp_clk", "gop_clk", "mg_clk", "mg_core_clk", "axi_clk";243 marvell,system-controller = <&cp0_syscon0>;244 245 ethernet-port@0 {246 interrupts = <ICU_GRP_NSR 39 IRQ_TYPE_LEVEL_HIGH>,247 <ICU_GRP_NSR 43 IRQ_TYPE_LEVEL_HIGH>,248 <ICU_GRP_NSR 47 IRQ_TYPE_LEVEL_HIGH>,249 <ICU_GRP_NSR 51 IRQ_TYPE_LEVEL_HIGH>,250 <ICU_GRP_NSR 55 IRQ_TYPE_LEVEL_HIGH>,251 <ICU_GRP_NSR 59 IRQ_TYPE_LEVEL_HIGH>,252 <ICU_GRP_NSR 63 IRQ_TYPE_LEVEL_HIGH>,253 <ICU_GRP_NSR 67 IRQ_TYPE_LEVEL_HIGH>,254 <ICU_GRP_NSR 71 IRQ_TYPE_LEVEL_HIGH>,255 <ICU_GRP_NSR 129 IRQ_TYPE_LEVEL_HIGH>;256 interrupt-names = "hif0", "hif1", "hif2", "hif3", "hif4",257 "hif5", "hif6", "hif7", "hif8", "link";258 phy-mode = "10gbase-r";259 phys = <&cp0_comphy4 0>;260 reg = <0>;261 port-id = <0>; /* For backward compatibility. */262 gop-port-id = <0>;263 };264 265 ethernet-port@1 {266 interrupts = <ICU_GRP_NSR 40 IRQ_TYPE_LEVEL_HIGH>,267 <ICU_GRP_NSR 44 IRQ_TYPE_LEVEL_HIGH>,268 <ICU_GRP_NSR 48 IRQ_TYPE_LEVEL_HIGH>,269 <ICU_GRP_NSR 52 IRQ_TYPE_LEVEL_HIGH>,270 <ICU_GRP_NSR 56 IRQ_TYPE_LEVEL_HIGH>,271 <ICU_GRP_NSR 60 IRQ_TYPE_LEVEL_HIGH>,272 <ICU_GRP_NSR 64 IRQ_TYPE_LEVEL_HIGH>,273 <ICU_GRP_NSR 68 IRQ_TYPE_LEVEL_HIGH>,274 <ICU_GRP_NSR 72 IRQ_TYPE_LEVEL_HIGH>,275 <ICU_GRP_NSR 128 IRQ_TYPE_LEVEL_HIGH>;276 interrupt-names = "hif0", "hif1", "hif2", "hif3", "hif4",277 "hif5", "hif6", "hif7", "hif8", "link";278 phy-mode = "rgmii-id";279 reg = <1>;280 port-id = <1>; /* For backward compatibility. */281 gop-port-id = <2>;282 };283 284 ethernet-port@2 {285 interrupts = <ICU_GRP_NSR 41 IRQ_TYPE_LEVEL_HIGH>,286 <ICU_GRP_NSR 45 IRQ_TYPE_LEVEL_HIGH>,287 <ICU_GRP_NSR 49 IRQ_TYPE_LEVEL_HIGH>,288 <ICU_GRP_NSR 53 IRQ_TYPE_LEVEL_HIGH>,289 <ICU_GRP_NSR 57 IRQ_TYPE_LEVEL_HIGH>,290 <ICU_GRP_NSR 61 IRQ_TYPE_LEVEL_HIGH>,291 <ICU_GRP_NSR 65 IRQ_TYPE_LEVEL_HIGH>,292 <ICU_GRP_NSR 69 IRQ_TYPE_LEVEL_HIGH>,293 <ICU_GRP_NSR 73 IRQ_TYPE_LEVEL_HIGH>,294 <ICU_GRP_NSR 127 IRQ_TYPE_LEVEL_HIGH>;295 interrupt-names = "hif0", "hif1", "hif2", "hif3", "hif4",296 "hif5", "hif6", "hif7", "hif8", "link";297 phy-mode = "2500base-x";298 managed = "in-band-status";299 phys = <&cp0_comphy5 2>;300 sfp = <&sfp_eth3>;301 reg = <2>;302 port-id = <2>; /* For backward compatibility. */303 gop-port-id = <3>;304 };305 };306