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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/net/mediatek,net.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: MediaTek Frame Engine Ethernet controller8 9maintainers:10 - Lorenzo Bianconi <lorenzo@kernel.org>11 - Felix Fietkau <nbd@nbd.name>12 13description:14 The frame engine ethernet controller can be found on MediaTek SoCs. These SoCs15 have dual GMAC ports.16 17properties:18 compatible:19 enum:20 - mediatek,mt2701-eth21 - mediatek,mt7623-eth22 - mediatek,mt7621-eth23 - mediatek,mt7622-eth24 - mediatek,mt7629-eth25 - mediatek,mt7981-eth26 - mediatek,mt7986-eth27 - mediatek,mt7988-eth28 - ralink,rt5350-eth29 30 reg:31 maxItems: 132 33 clocks:34 minItems: 235 maxItems: 2436 37 clock-names:38 minItems: 239 maxItems: 2440 41 interrupts:42 minItems: 143 maxItems: 444 45 power-domains:46 maxItems: 147 48 resets:49 maxItems: 350 51 reset-names:52 items:53 - const: fe54 - const: gmac55 - const: ppe56 57 mediatek,ethsys:58 $ref: /schemas/types.yaml#/definitions/phandle59 description:60 Phandle to the syscon node that handles the port setup.61 62 cci-control-port: true63 64 mediatek,hifsys:65 $ref: /schemas/types.yaml#/definitions/phandle66 description:67 Phandle to the mediatek hifsys controller used to provide various clocks68 and reset to the system.69 70 mediatek,infracfg:71 $ref: /schemas/types.yaml#/definitions/phandle72 description:73 Phandle to the syscon node that handles the path from GMAC to74 PHY variants.75 76 mediatek,pcie-mirror:77 $ref: /schemas/types.yaml#/definitions/phandle78 description:79 Phandle to the mediatek pcie-mirror controller.80 81 mediatek,pctl:82 $ref: /schemas/types.yaml#/definitions/phandle83 description:84 Phandle to the syscon node that handles the ports slew rate and85 driver current.86 87 mediatek,sgmiisys:88 $ref: /schemas/types.yaml#/definitions/phandle-array89 minItems: 190 maxItems: 291 items:92 maxItems: 193 description:94 A list of phandle to the syscon node that handles the SGMII setup which is required for95 those SoCs equipped with SGMII.96 97 mediatek,wed:98 $ref: /schemas/types.yaml#/definitions/phandle-array99 minItems: 2100 maxItems: 2101 items:102 maxItems: 1103 description:104 List of phandles to wireless ethernet dispatch nodes.105 106 mediatek,wed-pcie:107 $ref: /schemas/types.yaml#/definitions/phandle108 description:109 Phandle to the mediatek wed-pcie controller.110 111 dma-coherent: true112 113 mdio-bus:114 $ref: mdio.yaml#115 unevaluatedProperties: false116 117 "#address-cells":118 const: 1119 120 "#size-cells":121 const: 0122 123allOf:124 - $ref: ethernet-controller.yaml#125 - if:126 properties:127 compatible:128 contains:129 enum:130 - mediatek,mt2701-eth131 - mediatek,mt7623-eth132 then:133 properties:134 interrupts:135 minItems: 3136 maxItems: 3137 138 clocks:139 minItems: 4140 maxItems: 4141 142 clock-names:143 items:144 - const: ethif145 - const: esw146 - const: gp1147 - const: gp2148 149 mediatek,infracfg: false150 151 mediatek,wed: false152 153 mediatek,wed-pcie: false154 else:155 properties:156 mediatek,pctl: false157 158 - if:159 properties:160 compatible:161 contains:162 enum:163 - mediatek,mt7621-eth164 then:165 properties:166 interrupts:167 maxItems: 1168 169 clocks:170 minItems: 2171 maxItems: 2172 173 clock-names:174 items:175 - const: ethif176 - const: fe177 178 mediatek,infracfg: false179 180 mediatek,wed: false181 182 mediatek,wed-pcie: false183 184 - if:185 properties:186 compatible:187 contains:188 const: mediatek,mt7622-eth189 then:190 properties:191 interrupts:192 minItems: 3193 maxItems: 3194 195 clocks:196 minItems: 11197 maxItems: 11198 199 clock-names:200 items:201 - const: ethif202 - const: esw203 - const: gp0204 - const: gp1205 - const: gp2206 - const: sgmii_tx250m207 - const: sgmii_rx250m208 - const: sgmii_cdr_ref209 - const: sgmii_cdr_fb210 - const: sgmii_ck211 - const: eth2pll212 213 mediatek,infracfg: false214 215 mediatek,sgmiisys:216 minItems: 1217 maxItems: 1218 219 mediatek,wed-pcie: false220 else:221 properties:222 mediatek,pcie-mirror: false223 224 - if:225 properties:226 compatible:227 contains:228 const: mediatek,mt7629-eth229 then:230 properties:231 interrupts:232 minItems: 3233 maxItems: 3234 235 clocks:236 minItems: 17237 maxItems: 17238 239 clock-names:240 items:241 - const: ethif242 - const: sgmiitop243 - const: esw244 - const: gp0245 - const: gp1246 - const: gp2247 - const: fe248 - const: sgmii_tx250m249 - const: sgmii_rx250m250 - const: sgmii_cdr_ref251 - const: sgmii_cdr_fb252 - const: sgmii2_tx250m253 - const: sgmii2_rx250m254 - const: sgmii2_cdr_ref255 - const: sgmii2_cdr_fb256 - const: sgmii_ck257 - const: eth2pll258 259 mediatek,sgmiisys:260 minItems: 2261 maxItems: 2262 263 mediatek,wed: false264 265 mediatek,wed-pcie: false266 267 - if:268 properties:269 compatible:270 contains:271 const: mediatek,mt7981-eth272 then:273 properties:274 interrupts:275 minItems: 4276 277 clocks:278 minItems: 15279 maxItems: 15280 281 clock-names:282 items:283 - const: fe284 - const: gp2285 - const: gp1286 - const: wocpu0287 - const: sgmii_ck288 - const: sgmii_tx250m289 - const: sgmii_rx250m290 - const: sgmii_cdr_ref291 - const: sgmii_cdr_fb292 - const: sgmii2_tx250m293 - const: sgmii2_rx250m294 - const: sgmii2_cdr_ref295 - const: sgmii2_cdr_fb296 - const: netsys0297 - const: netsys1298 299 mediatek,infracfg: false300 301 mediatek,sgmiisys:302 minItems: 2303 maxItems: 2304 305 - if:306 properties:307 compatible:308 contains:309 const: mediatek,mt7986-eth310 then:311 properties:312 interrupts:313 minItems: 4314 315 clocks:316 minItems: 15317 maxItems: 15318 319 clock-names:320 items:321 - const: fe322 - const: gp2323 - const: gp1324 - const: wocpu1325 - const: wocpu0326 - const: sgmii_tx250m327 - const: sgmii_rx250m328 - const: sgmii_cdr_ref329 - const: sgmii_cdr_fb330 - const: sgmii2_tx250m331 - const: sgmii2_rx250m332 - const: sgmii2_cdr_ref333 - const: sgmii2_cdr_fb334 - const: netsys0335 - const: netsys1336 337 mediatek,infracfg: false338 339 mediatek,sgmiisys:340 minItems: 2341 maxItems: 2342 343 - if:344 properties:345 compatible:346 contains:347 const: mediatek,mt7988-eth348 then:349 properties:350 interrupts:351 minItems: 4352 353 clocks:354 minItems: 24355 maxItems: 24356 357 clock-names:358 items:359 - const: crypto360 - const: fe361 - const: gp2362 - const: gp1363 - const: gp3364 - const: ethwarp_wocpu2365 - const: ethwarp_wocpu1366 - const: ethwarp_wocpu0367 - const: esw368 - const: top_eth_gmii_sel369 - const: top_eth_refck_50m_sel370 - const: top_eth_sys_200m_sel371 - const: top_eth_sys_sel372 - const: top_eth_xgmii_sel373 - const: top_eth_mii_sel374 - const: top_netsys_sel375 - const: top_netsys_500m_sel376 - const: top_netsys_pao_2x_sel377 - const: top_netsys_sync_250m_sel378 - const: top_netsys_ppefb_250m_sel379 - const: top_netsys_warp_sel380 - const: xgp1381 - const: xgp2382 - const: xgp3383 384patternProperties:385 "^mac@[0-1]$":386 type: object387 unevaluatedProperties: false388 allOf:389 - $ref: ethernet-controller.yaml#390 description:391 Ethernet MAC node392 properties:393 compatible:394 const: mediatek,eth-mac395 396 reg:397 maxItems: 1398 399 required:400 - reg401 - compatible402 403required:404 - compatible405 - reg406 - interrupts407 - clocks408 - clock-names409 - mediatek,ethsys410 411unevaluatedProperties: false412 413examples:414 - |415 #include <dt-bindings/interrupt-controller/arm-gic.h>416 #include <dt-bindings/interrupt-controller/irq.h>417 #include <dt-bindings/clock/mt7622-clk.h>418 #include <dt-bindings/power/mt7622-power.h>419 420 soc {421 #address-cells = <2>;422 #size-cells = <2>;423 424 ethernet: ethernet@1b100000 {425 compatible = "mediatek,mt7622-eth";426 reg = <0 0x1b100000 0 0x20000>;427 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_LOW>,428 <GIC_SPI 224 IRQ_TYPE_LEVEL_LOW>,429 <GIC_SPI 225 IRQ_TYPE_LEVEL_LOW>;430 clocks = <&topckgen CLK_TOP_ETH_SEL>,431 <ðsys CLK_ETH_ESW_EN>,432 <ðsys CLK_ETH_GP0_EN>,433 <ðsys CLK_ETH_GP1_EN>,434 <ðsys CLK_ETH_GP2_EN>,435 <&sgmiisys CLK_SGMII_TX250M_EN>,436 <&sgmiisys CLK_SGMII_RX250M_EN>,437 <&sgmiisys CLK_SGMII_CDR_REF>,438 <&sgmiisys CLK_SGMII_CDR_FB>,439 <&topckgen CLK_TOP_SGMIIPLL>,440 <&apmixedsys CLK_APMIXED_ETH2PLL>;441 clock-names = "ethif", "esw", "gp0", "gp1", "gp2",442 "sgmii_tx250m", "sgmii_rx250m",443 "sgmii_cdr_ref", "sgmii_cdr_fb", "sgmii_ck",444 "eth2pll";445 power-domains = <&scpsys MT7622_POWER_DOMAIN_ETHSYS>;446 mediatek,ethsys = <ðsys>;447 mediatek,sgmiisys = <&sgmiisys>;448 cci-control-port = <&cci_control2>;449 mediatek,pcie-mirror = <&pcie_mirror>;450 mediatek,hifsys = <&hifsys>;451 dma-coherent;452 453 #address-cells = <1>;454 #size-cells = <0>;455 456 mdio0: mdio-bus {457 #address-cells = <1>;458 #size-cells = <0>;459 460 phy0: ethernet-phy@0 {461 reg = <0>;462 };463 464 phy1: ethernet-phy@1 {465 reg = <1>;466 };467 };468 469 gmac0: mac@0 {470 compatible = "mediatek,eth-mac";471 phy-mode = "rgmii";472 phy-handle = <&phy0>;473 reg = <0>;474 };475 476 gmac1: mac@1 {477 compatible = "mediatek,eth-mac";478 phy-mode = "rgmii";479 phy-handle = <&phy1>;480 reg = <1>;481 };482 };483 };484 485 - |486 #include <dt-bindings/interrupt-controller/arm-gic.h>487 #include <dt-bindings/interrupt-controller/irq.h>488 #include <dt-bindings/clock/mt7622-clk.h>489 490 soc {491 #address-cells = <2>;492 #size-cells = <2>;493 494 eth: ethernet@15100000 {495 #define CLK_ETH_FE_EN 0496 #define CLK_ETH_WOCPU1_EN 3497 #define CLK_ETH_WOCPU0_EN 4498 #define CLK_TOP_NETSYS_SEL 43499 #define CLK_TOP_NETSYS_500M_SEL 44500 #define CLK_TOP_NETSYS_2X_SEL 46501 #define CLK_TOP_SGM_325M_SEL 47502 #define CLK_APMIXED_NET2PLL 1503 #define CLK_APMIXED_SGMPLL 3504 505 compatible = "mediatek,mt7986-eth";506 reg = <0 0x15100000 0 0x80000>;507 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,508 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,509 <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,510 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;511 clocks = <ðsys CLK_ETH_FE_EN>,512 <ðsys CLK_ETH_GP2_EN>,513 <ðsys CLK_ETH_GP1_EN>,514 <ðsys CLK_ETH_WOCPU1_EN>,515 <ðsys CLK_ETH_WOCPU0_EN>,516 <&sgmiisys0 CLK_SGMII_TX250M_EN>,517 <&sgmiisys0 CLK_SGMII_RX250M_EN>,518 <&sgmiisys0 CLK_SGMII_CDR_REF>,519 <&sgmiisys0 CLK_SGMII_CDR_FB>,520 <&sgmiisys1 CLK_SGMII_TX250M_EN>,521 <&sgmiisys1 CLK_SGMII_RX250M_EN>,522 <&sgmiisys1 CLK_SGMII_CDR_REF>,523 <&sgmiisys1 CLK_SGMII_CDR_FB>,524 <&topckgen CLK_TOP_NETSYS_SEL>,525 <&topckgen CLK_TOP_NETSYS_SEL>;526 clock-names = "fe", "gp2", "gp1", "wocpu1", "wocpu0",527 "sgmii_tx250m", "sgmii_rx250m",528 "sgmii_cdr_ref", "sgmii_cdr_fb",529 "sgmii2_tx250m", "sgmii2_rx250m",530 "sgmii2_cdr_ref", "sgmii2_cdr_fb",531 "netsys0", "netsys1";532 mediatek,ethsys = <ðsys>;533 mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>;534 assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>,535 <&topckgen CLK_TOP_SGM_325M_SEL>;536 assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>,537 <&apmixedsys CLK_APMIXED_SGMPLL>;538 539 #address-cells = <1>;540 #size-cells = <0>;541 542 mdio: mdio-bus {543 #address-cells = <1>;544 #size-cells = <0>;545 546 phy5: ethernet-phy@0 {547 compatible = "ethernet-phy-id67c9.de0a";548 phy-mode = "2500base-x";549 reset-gpios = <&pio 6 1>;550 reset-deassert-us = <20000>;551 reg = <5>;552 };553 554 phy6: ethernet-phy@1 {555 compatible = "ethernet-phy-id67c9.de0a";556 phy-mode = "2500base-x";557 reg = <6>;558 };559 };560 561 mac0: mac@0 {562 compatible = "mediatek,eth-mac";563 phy-mode = "2500base-x";564 phy-handle = <&phy5>;565 reg = <0>;566 };567 568 mac1: mac@1 {569 compatible = "mediatek,eth-mac";570 phy-mode = "2500base-x";571 phy-handle = <&phy6>;572 reg = <1>;573 };574 };575 };576