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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/net/mediatek-dwmac.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: MediaTek DWMAC glue layer controller8 9maintainers:10 - Biao Huang <biao.huang@mediatek.com>11 12description:13 This file documents platform glue layer for stmmac.14 15# We need a select here so we don't match all nodes with 'snps,dwmac'16select:17 properties:18 compatible:19 contains:20 enum:21 - mediatek,mt2712-gmac22 - mediatek,mt8188-gmac23 - mediatek,mt8195-gmac24 required:25 - compatible26 27allOf:28 - $ref: snps,dwmac.yaml#29 30properties:31 compatible:32 oneOf:33 - items:34 - enum:35 - mediatek,mt2712-gmac36 - const: snps,dwmac-4.20a37 - items:38 - enum:39 - mediatek,mt8195-gmac40 - const: snps,dwmac-5.10a41 - items:42 - enum:43 - mediatek,mt8188-gmac44 - const: mediatek,mt8195-gmac45 - const: snps,dwmac-5.10a46 47 clocks:48 minItems: 549 items:50 - description: AXI clock51 - description: APB clock52 - description: MAC Main clock53 - description: PTP clock54 - description: RMII reference clock provided by MAC55 - description: MAC clock gate56 57 clock-names:58 minItems: 559 items:60 - const: axi61 - const: apb62 - const: mac_main63 - const: ptp_ref64 - const: rmii_internal65 - const: mac_cg66 67 power-domains:68 maxItems: 169 70 mediatek,pericfg:71 $ref: /schemas/types.yaml#/definitions/phandle72 description:73 The phandle to the syscon node that control ethernet74 interface and timing delay.75 76 mediatek,tx-delay-ps:77 description:78 The internal TX clock delay (provided by this driver) in nanoseconds.79 For MT2712 RGMII interface, Allowed value need to be a multiple of 170,80 or will round down. Range 0~31*170.81 For MT2712 RMII/MII interface, Allowed value need to be a multiple of 550,82 or will round down. Range 0~31*550.83 For MT8188/MT8195 RGMII/RMII/MII interface, Allowed value need to be a multiple of 290,84 or will round down. Range 0~31*290.85 86 mediatek,rx-delay-ps:87 description:88 The internal RX clock delay (provided by this driver) in nanoseconds.89 For MT2712 RGMII interface, Allowed value need to be a multiple of 170,90 or will round down. Range 0~31*170.91 For MT2712 RMII/MII interface, Allowed value need to be a multiple of 550,92 or will round down. Range 0~31*550.93 For MT8188/MT8195 RGMII/RMII/MII interface, Allowed value need to be a multiple94 of 290, or will round down. Range 0~31*290.95 96 mediatek,rmii-rxc:97 type: boolean98 description:99 If present, indicates that the RMII reference clock, which is from external100 PHYs, is connected to RXC pin. Otherwise, is connected to TXC pin.101 102 mediatek,rmii-clk-from-mac:103 type: boolean104 description:105 If present, indicates that MAC provides the RMII reference clock, which106 outputs to TXC pin only.107 108 mediatek,txc-inverse:109 type: boolean110 description:111 If present, indicates that112 1. tx clock will be inversed in MII/RGMII case,113 2. tx clock inside MAC will be inversed relative to reference clock114 which is from external PHYs in RMII case, and it rarely happen.115 3. the reference clock, which outputs to TXC pin will be inversed in RMII case116 when the reference clock is from MAC.117 118 mediatek,rxc-inverse:119 type: boolean120 description:121 If present, indicates that122 1. rx clock will be inversed in MII/RGMII case.123 2. reference clock will be inversed when arrived at MAC in RMII case, when124 the reference clock is from external PHYs.125 3. the inside clock, which be sent to MAC, will be inversed in RMII case when126 the reference clock is from MAC.127 128 mediatek,mac-wol:129 type: boolean130 description:131 If present, indicates that MAC supports WOL(Wake-On-LAN), and MAC WOL will be enabled.132 Otherwise, PHY WOL is preferred.133 134required:135 - compatible136 - reg137 - interrupts138 - interrupt-names139 - clocks140 - clock-names141 - phy-mode142 - mediatek,pericfg143 144unevaluatedProperties: false145 146examples:147 - |148 #include <dt-bindings/clock/mt2712-clk.h>149 #include <dt-bindings/gpio/gpio.h>150 #include <dt-bindings/interrupt-controller/arm-gic.h>151 #include <dt-bindings/interrupt-controller/irq.h>152 #include <dt-bindings/power/mt2712-power.h>153 154 eth: ethernet@1101c000 {155 compatible = "mediatek,mt2712-gmac", "snps,dwmac-4.20a";156 reg = <0x1101c000 0x1300>;157 interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_LOW>;158 interrupt-names = "macirq";159 phy-mode = "rgmii-rxid";160 mac-address = [00 55 7b b5 7d f7];161 clock-names = "axi",162 "apb",163 "mac_main",164 "ptp_ref",165 "rmii_internal";166 clocks = <&pericfg CLK_PERI_GMAC>,167 <&pericfg CLK_PERI_GMAC_PCLK>,168 <&topckgen CLK_TOP_ETHER_125M_SEL>,169 <&topckgen CLK_TOP_ETHER_50M_SEL>,170 <&topckgen CLK_TOP_ETHER_50M_RMII_SEL>;171 assigned-clocks = <&topckgen CLK_TOP_ETHER_125M_SEL>,172 <&topckgen CLK_TOP_ETHER_50M_SEL>,173 <&topckgen CLK_TOP_ETHER_50M_RMII_SEL>;174 assigned-clock-parents = <&topckgen CLK_TOP_ETHERPLL_125M>,175 <&topckgen CLK_TOP_APLL1_D3>,176 <&topckgen CLK_TOP_ETHERPLL_50M>;177 power-domains = <&scpsys MT2712_POWER_DOMAIN_AUDIO>;178 mediatek,pericfg = <&pericfg>;179 mediatek,tx-delay-ps = <1530>;180 snps,txpbl = <1>;181 snps,rxpbl = <1>;182 snps,reset-gpio = <&pio 87 GPIO_ACTIVE_LOW>;183 snps,reset-delays-us = <0 10000 10000>;184 };185