72 lines · yaml
1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause2%YAML 1.23---4$id: http://devicetree.org/schemas/net/mscc,miim.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Microsemi MII Management Controller (MIIM)8 9maintainers:10 - Alexandre Belloni <alexandre.belloni@bootlin.com>11 12allOf:13 - $ref: mdio.yaml#14 15properties:16 compatible:17 enum:18 - mscc,ocelot-miim19 - microchip,lan966x-miim20 21 "#address-cells":22 const: 123 24 "#size-cells":25 const: 026 27 reg:28 items:29 - description: base address30 - description: associated reset register for internal PHYs31 minItems: 132 33 interrupts:34 maxItems: 135 36 clocks:37 maxItems: 138 39 clock-frequency: true40 41 resets:42 items:43 - description:44 Reset shared with all blocks attached to the Switch Core Register45 Bus (CSR) including VRAP slave.46 47 reset-names:48 items:49 - const: switch50 51required:52 - compatible53 - reg54 - "#address-cells"55 - "#size-cells"56 57unevaluatedProperties: false58 59examples:60 - |61 mdio@107009c {62 compatible = "mscc,ocelot-miim";63 reg = <0x107009c 0x36>, <0x10700f0 0x8>;64 interrupts = <14>;65 #address-cells = <1>;66 #size-cells = <0>;67 68 phy0: ethernet-phy@0 {69 reg = <0>;70 };71 };72