103 lines · yaml
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/net/pcs/mediatek,sgmiisys.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: MediaTek SGMIISYS Controller8 9maintainers:10 - Matthias Brugger <matthias.bgg@gmail.com>11 12description:13 The MediaTek SGMIISYS controller provides a SGMII PCS and some clocks14 to the ethernet subsystem to which it is attached.15 16properties:17 compatible:18 oneOf:19 - items:20 - enum:21 - mediatek,mt7622-sgmiisys22 - mediatek,mt7629-sgmiisys23 - mediatek,mt7981-sgmiisys_024 - mediatek,mt7981-sgmiisys_125 - mediatek,mt7986-sgmiisys_026 - mediatek,mt7986-sgmiisys_127 - const: syscon28 - items:29 - enum:30 - mediatek,mt7988-sgmiisys031 - mediatek,mt7988-sgmiisys132 - const: simple-mfd33 - const: syscon34 35 reg:36 maxItems: 137 38 '#clock-cells':39 const: 140 41 mediatek,pnswap:42 description: Invert polarity of the SGMII data lanes43 type: boolean44 45 pcs:46 type: object47 description: MediaTek LynxI HSGMII PCS48 properties:49 compatible:50 const: mediatek,mt7988-sgmii51 52 clocks:53 maxItems: 354 55 clock-names:56 items:57 - const: sgmii_sel58 - const: sgmii_tx59 - const: sgmii_rx60 61 required:62 - compatible63 - clocks64 - clock-names65 66 additionalProperties: false67 68required:69 - compatible70 - reg71 - '#clock-cells'72 73allOf:74 - if:75 properties:76 compatible:77 contains:78 enum:79 - mediatek,mt7988-sgmiisys080 - mediatek,mt7988-sgmiisys181 82 then:83 required:84 - pcs85 86 else:87 properties:88 pcs: false89 90additionalProperties: false91 92examples:93 - |94 soc {95 #address-cells = <2>;96 #size-cells = <2>;97 sgmiisys: syscon@1b128000 {98 compatible = "mediatek,mt7622-sgmiisys", "syscon";99 reg = <0 0x1b128000 0 0x1000>;100 #clock-cells = <1>;101 };102 };103