137 lines · yaml
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/net/pcs/snps,dw-xpcs.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Synopsys DesignWare Ethernet PCS8 9maintainers:10 - Serge Semin <fancer.lancer@gmail.com>11 12description:13 Synopsys DesignWare Ethernet Physical Coding Sublayer provides an interface14 between Media Access Control and Physical Medium Attachment Sublayer through15 the Media Independent Interface (XGMII, USXGMII, XLGMII, GMII, etc)16 controlled by means of the IEEE std. Clause 45 registers set. The PCS can be17 optionally synthesized with a vendor-specific interface connected to18 Synopsys PMA (also called DesignWare Consumer/Enterprise PHY) although in19 general it can be used to communicate with any compatible PHY.20 21 The PCS CSRs can be accessible either over the Ethernet MDIO bus or directly22 by means of the APB3/MCI interfaces. In the later case the XPCS can be mapped23 right to the system IO memory space.24 25properties:26 compatible:27 oneOf:28 - description: Synopsys DesignWare XPCS with none or unknown PMA29 const: snps,dw-xpcs30 - description: Synopsys DesignWare XPCS with Consumer Gen1 3G PMA31 const: snps,dw-xpcs-gen1-3g32 - description: Synopsys DesignWare XPCS with Consumer Gen2 3G PMA33 const: snps,dw-xpcs-gen2-3g34 - description: Synopsys DesignWare XPCS with Consumer Gen2 6G PMA35 const: snps,dw-xpcs-gen2-6g36 - description: Synopsys DesignWare XPCS with Consumer Gen4 3G PMA37 const: snps,dw-xpcs-gen4-3g38 - description: Synopsys DesignWare XPCS with Consumer Gen4 6G PMA39 const: snps,dw-xpcs-gen4-6g40 - description: Synopsys DesignWare XPCS with Consumer Gen5 10G PMA41 const: snps,dw-xpcs-gen5-10g42 - description: Synopsys DesignWare XPCS with Consumer Gen5 12G PMA43 const: snps,dw-xpcs-gen5-12g44 45 reg:46 items:47 - description:48 In case of the MDIO management interface this just a 5-bits ID49 of the MDIO bus device. If DW XPCS CSRs space is accessed over the50 MCI or APB3 management interfaces, then the space mapping can be51 either 'direct' or 'indirect'. In the former case all Clause 4552 registers are contiguously mapped within the address space53 MMD '[20:16]', Reg '[15:0]'. In the later case the space is divided54 to the multiple 256 register sets. There is a special viewport CSR55 which is responsible for the set selection. The upper part of56 the CSR address MMD+REG[20:8] is supposed to be written in there57 so the corresponding subset would be mapped to the lowest 255 CSRs.58 59 reg-names:60 items:61 - enum: [ direct, indirect ]62 63 reg-io-width:64 description:65 The way the CSRs are mapped to the memory is platform depended. Since66 each Clause 45 CSR is of 16-bits wide the access instructions must be67 two bytes aligned at least.68 default: 269 enum: [ 2, 4 ]70 71 interrupts:72 description:73 System interface interrupt output (sbd_intr_o) indicating Clause 73/3774 auto-negotiation events':' Page received, AN is completed or incompatible75 link partner.76 maxItems: 177 78 clocks:79 description:80 The MCI and APB3 interfaces are supposed to be equipped with a clock81 source connected to the clk_csr_i line.82 83 PCS/PMA layer can be clocked by an internal reference clock source84 (phyN_core_refclk) or by an externally connected (phyN_pad_refclk) clock85 generator. Both clocks can be supplied at a time.86 minItems: 187 maxItems: 388 89 clock-names:90 oneOf:91 - minItems: 192 items: # MDIO93 - enum: [core, pad]94 - const: pad95 - minItems: 196 items: # MCI or APB97 - const: csr98 - enum: [core, pad]99 - const: pad100 101required:102 - compatible103 - reg104 105additionalProperties: false106 107examples:108 - |109 #include <dt-bindings/interrupt-controller/irq.h>110 111 ethernet-pcs@1f05d000 {112 compatible = "snps,dw-xpcs";113 reg = <0x1f05d000 0x1000>;114 reg-names = "indirect";115 116 reg-io-width = <4>;117 118 interrupts = <79 IRQ_TYPE_LEVEL_HIGH>;119 120 clocks = <&ccu_pclk>, <&ccu_core>, <&ccu_pad>;121 clock-names = "csr", "core", "pad";122 };123 - |124 mdio-bus {125 #address-cells = <1>;126 #size-cells = <0>;127 128 ethernet-pcs@0 {129 compatible = "snps,dw-xpcs";130 reg = <0>;131 132 clocks = <&ccu_core>, <&ccu_pad>;133 clock-names = "core", "pad";134 };135 };136...137