177 lines · yaml
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/net/pse-pd/microchip,pd692x0.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Microchip PD692x0 Power Sourcing Equipment controller8 9maintainers:10 - Kory Maincent <kory.maincent@bootlin.com>11 12allOf:13 - $ref: pse-controller.yaml#14 15properties:16 compatible:17 enum:18 - microchip,pd6920019 - microchip,pd6921020 - microchip,pd6922021 22 reg:23 maxItems: 124 25 managers:26 type: object27 additionalProperties: false28 description:29 List of the PD69208T4/PD69204T4/PD69208M PSE managers. Each manager30 have 4 or 8 physical ports according to the chip version. No need to31 specify the SPI chip select as it is automatically detected by the32 PD692x0 PSE controller. The PSE managers have to be described from33 the lowest chip select to the greatest one, which is the detection34 behavior of the PD692x0 PSE controller. The PD692x0 support up to35 12 PSE managers which can expose up to 96 physical ports. All36 physical ports available on a manager have to be described in the37 incremental order even if they are not used.38 39 properties:40 "#address-cells":41 const: 142 43 "#size-cells":44 const: 045 46 required:47 - "#address-cells"48 - "#size-cells"49 50 patternProperties:51 "^manager@[0-9a-b]$":52 type: object53 additionalProperties: false54 description:55 PD69208T4/PD69204T4/PD69208M PSE manager exposing 4 or 8 physical56 ports.57 58 properties:59 reg:60 description:61 Incremental index of the PSE manager starting from 0, ranging62 from lowest to highest chip select, up to 11.63 maxItems: 164 65 "#address-cells":66 const: 167 68 "#size-cells":69 const: 070 71 patternProperties:72 '^port@[0-7]$':73 type: object74 additionalProperties: false75 76 properties:77 reg:78 maxItems: 179 80 required:81 - reg82 83 required:84 - reg85 - "#address-cells"86 - "#size-cells"87 88required:89 - compatible90 - reg91 - pse-pis92 93unevaluatedProperties: false94 95examples:96 - |97 i2c {98 #address-cells = <1>;99 #size-cells = <0>;100 101 ethernet-pse@3c {102 compatible = "microchip,pd69200";103 reg = <0x3c>;104 105 managers {106 #address-cells = <1>;107 #size-cells = <0>;108 109 manager@0 {110 reg = <0>;111 #address-cells = <1>;112 #size-cells = <0>;113 114 phys0: port@0 {115 reg = <0>;116 };117 118 phys1: port@1 {119 reg = <1>;120 };121 122 phys2: port@2 {123 reg = <2>;124 };125 126 phys3: port@3 {127 reg = <3>;128 };129 };130 131 manager@1 {132 reg = <1>;133 #address-cells = <1>;134 #size-cells = <0>;135 136 phys4: port@0 {137 reg = <0>;138 };139 140 phys5: port@1 {141 reg = <1>;142 };143 144 phys6: port@2 {145 reg = <2>;146 };147 148 phys7: port@3 {149 reg = <3>;150 };151 };152 };153 154 pse-pis {155 #address-cells = <1>;156 #size-cells = <0>;157 158 pse_pi0: pse-pi@0 {159 reg = <0>;160 #pse-cells = <0>;161 pairset-names = "alternative-a", "alternative-b";162 pairsets = <&phys0>, <&phys1>;163 polarity-supported = "MDI", "S";164 vpwr-supply = <&vpwr1>;165 };166 pse_pi1: pse-pi@1 {167 reg = <1>;168 #pse-cells = <0>;169 pairset-names = "alternative-a";170 pairsets = <&phys2>;171 polarity-supported = "MDI";172 vpwr-supply = <&vpwr2>;173 };174 };175 };176 };177