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1Altera SOCFPGA SoC DWMAC controller2 3This is a variant of the dwmac/stmmac driver an inherits all descriptions4present in Documentation/devicetree/bindings/net/stmmac.txt.5 6The device node has additional properties:7 8Required properties:9 - compatible : For Cyclone5/Arria5 SoCs it should contain10 "altr,socfpga-stmmac". For Arria10/Agilex/Stratix10 SoCs11 "altr,socfpga-stmmac-a10-s10".12 Along with "snps,dwmac" and any applicable more detailed13 designware version numbers documented in stmmac.txt14 - altr,sysmgr-syscon : Should be the phandle to the system manager node that15 encompasses the glue register, the register offset, and the register shift.16 On Cyclone5/Arria5, the register shift represents the PHY mode bits, while17 on the Arria10/Stratix10/Agilex platforms, the register shift represents18 bit for each emac to enable/disable signals from the FPGA fabric to the19 EMAC modules.20 - altr,f2h_ptp_ref_clk use f2h_ptp_ref_clk instead of default eosc1 clock21 for ptp ref clk. This affects all emacs as the clock is common.22 23Optional properties:24altr,emac-splitter: Should be the phandle to the emac splitter soft IP node if25 DWMAC controller is connected emac splitter.26phy-mode: The phy mode the ethernet operates in27altr,sgmii-to-sgmii-converter: phandle to the TSE SGMII converter28 29This device node has additional phandle dependency, the sgmii converter:30 31Required properties:32 - compatible : Should be altr,gmii-to-sgmii-2.033 - reg-names : Should be "eth_tse_control_port"34 35Example:36 37gmii_to_sgmii_converter: phy@100000240 {38 compatible = "altr,gmii-to-sgmii-2.0";39 reg = <0x00000001 0x00000240 0x00000008>,40 <0x00000001 0x00000200 0x00000040>;41 reg-names = "eth_tse_control_port";42 clocks = <&sgmii_1_clk_0 &emac1 1 &sgmii_clk_125 &sgmii_clk_125>;43 clock-names = "tse_pcs_ref_clk_clock_connection", "tse_rx_cdr_refclk";44};45 46gmac0: ethernet@ff700000 {47 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";48 altr,sysmgr-syscon = <&sysmgr 0x60 0>;49 reg = <0xff700000 0x2000>;50 interrupts = <0 115 4>;51 interrupt-names = "macirq";52 mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */53 clocks = <&emac_0_clk>;54 clock-names = "stmmaceth";55 phy-mode = "sgmii";56 altr,gmii-to-sgmii-converter = <&gmii_to_sgmii_converter>;57};58