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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/net/ti,cpsw-switch.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: TI SoC Ethernet Switch Controller (CPSW)8 9maintainers:10 - Siddharth Vadapalli <s-vadapalli@ti.com>11 - Roger Quadros <rogerq@kernel.org>12 13description:14 The 3-port switch gigabit ethernet subsystem provides ethernet packet15 communication and can be configured as an ethernet switch. It provides the16 gigabit media independent interface (GMII),reduced gigabit media17 independent interface (RGMII), reduced media independent interface (RMII),18 the management data input output (MDIO) for physical layer device (PHY)19 management.20 21properties:22 compatible:23 oneOf:24 - const: ti,cpsw-switch25 - items:26 - const: ti,am335x-cpsw-switch27 - const: ti,cpsw-switch28 - items:29 - const: ti,am4372-cpsw-switch30 - const: ti,cpsw-switch31 - items:32 - const: ti,dra7-cpsw-switch33 - const: ti,cpsw-switch34 35 reg:36 maxItems: 137 description:38 The physical base address and size of full the CPSW module IO range39 40 '#address-cells':41 const: 142 43 '#size-cells':44 const: 145 46 ranges: true47 48 clocks:49 maxItems: 150 description: CPSW functional clock51 52 clock-names:53 items:54 - const: fck55 56 interrupts:57 items:58 - description: RX_THRESH interrupt59 - description: RX interrupt60 - description: TX interrupt61 - description: MISC interrupt62 63 interrupt-names:64 items:65 - const: rx_thresh66 - const: rx67 - const: tx68 - const: misc69 70 pinctrl-names: true71 72 syscon:73 $ref: /schemas/types.yaml#/definitions/phandle74 description:75 Phandle to the system control device node which provides access to76 efuse IO range with MAC addresses77 78 ethernet-ports:79 type: object80 additionalProperties: false81 82 properties:83 '#address-cells':84 const: 185 '#size-cells':86 const: 087 88 patternProperties:89 "^port@[12]$":90 type: object91 description: CPSW external ports92 93 $ref: ethernet-controller.yaml#94 unevaluatedProperties: false95 96 properties:97 reg:98 items:99 - enum: [1, 2]100 description: CPSW port number101 102 phys:103 maxItems: 1104 description: phandle on phy-gmii-sel PHY105 106 label:107 description: label associated with this port108 109 ti,dual-emac-pvid:110 $ref: /schemas/types.yaml#/definitions/uint32111 minimum: 1112 maximum: 1024113 description:114 Specifies default PORT VID to be used to segregate115 ports. Default value - CPSW port number.116 117 required:118 - reg119 - phys120 121 cpts:122 type: object123 unevaluatedProperties: false124 description:125 The Common Platform Time Sync (CPTS) module126 127 properties:128 clocks:129 maxItems: 1130 description: CPTS reference clock131 132 clock-names:133 items:134 - const: cpts135 136 cpts_clock_mult:137 $ref: /schemas/types.yaml#/definitions/uint32138 description:139 Numerator to convert input clock ticks into ns140 141 cpts_clock_shift:142 $ref: /schemas/types.yaml#/definitions/uint32143 description:144 Denominator to convert input clock ticks into ns.145 Mult and shift will be calculated basing on CPTS rftclk frequency if146 both cpts_clock_shift and cpts_clock_mult properties are not provided.147 148 required:149 - clocks150 - clock-names151 152patternProperties:153 "^mdio@":154 type: object155 description:156 CPSW MDIO bus.157 $ref: ti,davinci-mdio.yaml#158 159 160required:161 - compatible162 - reg163 - ranges164 - clocks165 - clock-names166 - interrupts167 - interrupt-names168 - '#address-cells'169 - '#size-cells'170 171additionalProperties: false172 173examples:174 - |175 #include <dt-bindings/interrupt-controller/irq.h>176 #include <dt-bindings/interrupt-controller/arm-gic.h>177 #include <dt-bindings/clock/dra7.h>178 179 mac_sw: switch@0 {180 compatible = "ti,dra7-cpsw-switch","ti,cpsw-switch";181 reg = <0x0 0x4000>;182 ranges = <0 0 0x4000>;183 clocks = <&gmac_main_clk>;184 clock-names = "fck";185 #address-cells = <1>;186 #size-cells = <1>;187 syscon = <&scm_conf>;188 189 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,190 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,191 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,192 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>;193 interrupt-names = "rx_thresh", "rx", "tx", "misc";194 195 ethernet-ports {196 #address-cells = <1>;197 #size-cells = <0>;198 199 cpsw_port1: port@1 {200 reg = <1>;201 label = "port1";202 mac-address = [ 00 00 00 00 00 00 ];203 phys = <&phy_gmii_sel 1>;204 phy-handle = <ðphy0_sw>;205 phy-mode = "rgmii";206 ti,dual-emac-pvid = <1>;207 };208 209 cpsw_port2: port@2 {210 reg = <2>;211 label = "wan";212 mac-address = [ 00 00 00 00 00 00 ];213 phys = <&phy_gmii_sel 2>;214 phy-handle = <ðphy1_sw>;215 phy-mode = "rgmii";216 ti,dual-emac-pvid = <2>;217 };218 };219 220 davinci_mdio_sw: mdio@1000 {221 compatible = "ti,cpsw-mdio","ti,davinci_mdio";222 reg = <0x1000 0x100>;223 clocks = <&gmac_clkctrl DRA7_GMAC_GMAC_CLKCTRL 0>;224 clock-names = "fck";225 #address-cells = <1>;226 #size-cells = <0>;227 bus_freq = <1000000>;228 229 ethphy0_sw: ethernet-phy@0 {230 reg = <0>;231 };232 233 ethphy1_sw: ethernet-phy@1 {234 reg = <1>;235 };236 };237 238 cpts {239 clocks = <&gmac_clkctrl DRA7_GMAC_GMAC_CLKCTRL 25>;240 clock-names = "cpts";241 };242 };243