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1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/nvmem/rockchip,otp.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Rockchip internal OTP (One Time Programmable) memory8 9maintainers:10  - Heiko Stuebner <heiko@sntech.de>11 12properties:13  compatible:14    enum:15      - rockchip,px30-otp16      - rockchip,rk3308-otp17      - rockchip,rk3588-otp18 19  reg:20    maxItems: 121 22  clocks:23    minItems: 324    maxItems: 425 26  clock-names:27    minItems: 328    items:29      - const: otp30      - const: apb_pclk31      - const: phy32      - const: arb33 34  resets:35    minItems: 136    maxItems: 337 38  reset-names:39    minItems: 140    maxItems: 341 42required:43  - compatible44  - reg45  - clocks46  - clock-names47  - resets48  - reset-names49 50allOf:51  - $ref: nvmem.yaml#52  - $ref: nvmem-deprecated-cells.yaml#53 54  - if:55      properties:56        compatible:57          contains:58            enum:59              - rockchip,px30-otp60              - rockchip,rk3308-otp61    then:62      properties:63        clocks:64          maxItems: 365        resets:66          maxItems: 167        reset-names:68          items:69            - const: phy70 71  - if:72      properties:73        compatible:74          contains:75            enum:76              - rockchip,rk3588-otp77    then:78      properties:79        clocks:80          minItems: 481        resets:82          minItems: 383        reset-names:84          items:85            - const: otp86            - const: apb87            - const: arb88 89unevaluatedProperties: false90 91examples:92  - |93    #include <dt-bindings/clock/px30-cru.h>94 95    soc {96        #address-cells = <2>;97        #size-cells = <2>;98 99        otp: efuse@ff290000 {100            compatible = "rockchip,px30-otp";101            reg = <0x0 0xff290000 0x0 0x4000>;102            clocks = <&cru SCLK_OTP_USR>, <&cru PCLK_OTP_NS>,103                     <&cru PCLK_OTP_PHY>;104            clock-names = "otp", "apb_pclk", "phy";105            resets = <&cru SRST_OTP_PHY>;106            reset-names = "phy";107            #address-cells = <1>;108            #size-cells = <1>;109 110            cpu_id: id@7 {111                reg = <0x07 0x10>;112            };113 114            cpu_leakage: cpu-leakage@17 {115                reg = <0x17 0x1>;116            };117 118            performance: performance@1e {119                reg = <0x1e 0x1>;120                bits = <4 3>;121            };122        };123    };124