135 lines · yaml
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/pci/amlogic,axg-pcie.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Amlogic Meson AXG DWC PCIe SoC controller8 9maintainers:10 - Neil Armstrong <neil.armstrong@linaro.org>11 12description:13 Amlogic Meson PCIe host controller is based on the Synopsys DesignWare PCI core.14 15allOf:16 - $ref: /schemas/pci/pci-host-bridge.yaml#17 - $ref: /schemas/pci/snps,dw-pcie-common.yaml#18 19# We need a select here so we don't match all nodes with 'snps,dw-pcie'20select:21 properties:22 compatible:23 enum:24 - amlogic,axg-pcie25 - amlogic,g12a-pcie26 required:27 - compatible28 29properties:30 compatible:31 items:32 - enum:33 - amlogic,axg-pcie34 - amlogic,g12a-pcie35 - const: snps,dw-pcie36 37 reg:38 items:39 - description: External local bus interface registers40 - description: Meson designed configuration registers41 - description: PCIe configuration space42 43 reg-names:44 items:45 - const: elbi46 - const: cfg47 - const: config48 49 interrupts:50 maxItems: 151 52 clocks:53 items:54 - description: PCIe GEN 100M PLL clock55 - description: PCIe RC clock gate56 - description: PCIe PHY clock57 58 clock-names:59 items:60 - const: pclk61 - const: port62 - const: general63 64 phys:65 maxItems: 166 67 phy-names:68 const: pcie69 70 resets:71 items:72 - description: Port Reset73 - description: Shared APB reset74 75 reset-names:76 items:77 - const: port78 - const: apb79 80 num-lanes:81 const: 182 83 power-domains:84 maxItems: 185 86required:87 - compatible88 - reg89 - reg-names90 - interrupts91 - clock92 - clock-names93 - "#address-cells"94 - "#size-cells"95 - "#interrupt-cells"96 - interrupt-map97 - interrupt-map-mask98 - ranges99 - bus-range100 - device_type101 - num-lanes102 - phys103 - phy-names104 - resets105 - reset-names106 107unevaluatedProperties: false108 109examples:110 - |111 #include <dt-bindings/interrupt-controller/irq.h>112 #include <dt-bindings/interrupt-controller/arm-gic.h>113 pcie: pcie@f9800000 {114 compatible = "amlogic,axg-pcie", "snps,dw-pcie";115 reg = <0xf9800000 0x400000>, <0xff646000 0x2000>, <0xf9f00000 0x100000>;116 reg-names = "elbi", "cfg", "config";117 interrupts = <GIC_SPI 177 IRQ_TYPE_EDGE_RISING>;118 clocks = <&pclk>, <&clk_port>, <&clk_phy>;119 clock-names = "pclk", "port", "general";120 resets = <&reset_pcie_port>, <&reset_pcie_apb>;121 reset-names = "port", "apb";122 phys = <&pcie_phy>;123 phy-names = "pcie";124 #interrupt-cells = <1>;125 interrupt-map-mask = <0 0 0 0>;126 interrupt-map = <0 0 0 0 &gic GIC_SPI 179 IRQ_TYPE_EDGE_RISING>;127 bus-range = <0x0 0xff>;128 #address-cells = <3>;129 #size-cells = <2>;130 device_type = "pci";131 num-lanes = <1>;132 ranges = <0x82000000 0 0 0xf9c00000 0 0x00300000>;133 };134...135