256 lines · yaml
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/pci/fsl,imx6q-pcie-common.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Freescale i.MX6 PCIe RC/EP controller8 9maintainers:10 - Lucas Stach <l.stach@pengutronix.de>11 - Richard Zhu <hongxing.zhu@nxp.com>12 13description:14 Generic Freescale i.MX PCIe Root Port and Endpoint controller15 properties.16 17properties:18 clocks:19 minItems: 320 maxItems: 421 22 clock-names:23 minItems: 324 maxItems: 425 26 num-lanes:27 const: 128 29 fsl,imx7d-pcie-phy:30 $ref: /schemas/types.yaml#/definitions/phandle31 description: A phandle to an fsl,imx7d-pcie-phy node. Additional32 required properties for imx7d-pcie, imx7d-pcie-ep, imx8mq-pcie,33 and imx8mq-pcie-ep.34 35 power-domains:36 minItems: 137 items:38 - description: The phandle pointing to the DISPLAY domain for39 imx6sx-pcie, imx6sx-pcie-ep, to PCIE_PHY power domain for40 imx7d-pcie, imx7d-pcie-ep, imx8mq-pcie and imx8mq-pcie-ep.41 - description: The phandle pointing to the PCIE_PHY power domains42 for imx6sx-pcie and imx6sx-pcie-ep.43 44 power-domain-names:45 minItems: 146 items:47 - const: pcie48 - const: pcie_phy49 50 resets:51 minItems: 252 maxItems: 353 description: Phandles to PCIe-related reset lines exposed by SRC54 IP block. Additional required by imx7d-pcie, imx7d-pcie-ep,55 imx8mq-pcie, and imx8mq-pcie-ep.56 57 reset-names:58 minItems: 259 maxItems: 360 61 fsl,tx-deemph-gen1:62 description: Gen1 De-emphasis value (optional required).63 $ref: /schemas/types.yaml#/definitions/uint3264 default: 065 66 fsl,tx-deemph-gen2-3p5db:67 description: Gen2 (3.5db) De-emphasis value (optional required).68 $ref: /schemas/types.yaml#/definitions/uint3269 default: 070 71 fsl,tx-deemph-gen2-6db:72 description: Gen2 (6db) De-emphasis value (optional required).73 $ref: /schemas/types.yaml#/definitions/uint3274 default: 2075 76 fsl,tx-swing-full:77 description: Gen2 TX SWING FULL value (optional required).78 $ref: /schemas/types.yaml#/definitions/uint3279 default: 12780 81 fsl,tx-swing-low:82 description: TX launch amplitude swing_low value (optional required).83 $ref: /schemas/types.yaml#/definitions/uint3284 default: 12785 86 fsl,max-link-speed:87 description: Specify PCI Gen for link capability (optional required).88 Note that the IMX6 LVDS clock outputs do not meet gen2 jitter89 requirements and thus for gen2 capability a gen2 compliant clock90 generator should be used and configured.91 $ref: /schemas/types.yaml#/definitions/uint3292 enum: [1, 2, 3, 4]93 default: 194 95 phys:96 maxItems: 197 98 phy-names:99 const: pcie-phy100 101 vpcie-supply:102 description: Should specify the regulator in charge of PCIe port power.103 The regulator will be enabled when initializing the PCIe host and104 disabled either as part of the init process or when shutting down105 the host (optional required).106 107 vph-supply:108 description: Should specify the regulator in charge of VPH one of109 the three PCIe PHY powers. This regulator can be supplied by both110 1.8v and 3.3v voltage supplies (optional required).111 112required:113 - clocks114 - clock-names115 - num-lanes116 117allOf:118 - if:119 properties:120 compatible:121 contains:122 enum:123 - fsl,imx6sx-pcie124 - fsl,imx6sx-pcie-ep125 then:126 properties:127 clock-names:128 items:129 - {}130 - {}131 - const: pcie_phy132 - const: pcie_inbound_axi133 power-domains:134 minItems: 2135 power-domain-names:136 minItems: 2137 138 - if:139 properties:140 compatible:141 contains:142 enum:143 - fsl,imx8mq-pcie144 - fsl,imx8mq-pcie-ep145 then:146 properties:147 clock-names:148 items:149 - {}150 - {}151 - const: pcie_phy152 - const: pcie_aux153 154 - if:155 properties:156 compatible:157 contains:158 enum:159 - fsl,imx6q-pcie160 - fsl,imx6qp-pcie161 - fsl,imx7d-pcie162 - fsl,imx6q-pcie-ep163 - fsl,imx6qp-pcie-ep164 - fsl,imx7d-pcie-ep165 then:166 properties:167 clock-names:168 maxItems: 3169 contains:170 const: pcie_phy171 172 - if:173 properties:174 compatible:175 contains:176 enum:177 - fsl,imx8mm-pcie178 - fsl,imx8mp-pcie179 - fsl,imx8mm-pcie-ep180 - fsl,imx8mp-pcie-ep181 then:182 properties:183 clock-names:184 maxItems: 3185 contains:186 const: pcie_aux187 - if:188 properties:189 compatible:190 contains:191 enum:192 - fsl,imx6q-pcie193 - fsl,imx6qp-pcie194 - fsl,imx6q-pcie-ep195 - fsl,imx6qp-pcie-ep196 then:197 properties:198 power-domains: false199 power-domain-names: false200 201 - if:202 not:203 properties:204 compatible:205 contains:206 enum:207 - fsl,imx6sx-pcie208 - fsl,imx6q-pcie209 - fsl,imx6qp-pcie210 - fsl,imx95-pcie211 - fsl,imx6sx-pcie-ep212 - fsl,imx6q-pcie-ep213 - fsl,imx6qp-pcie-ep214 then:215 properties:216 power-domains:217 maxItems: 1218 power-domain-names: false219 220 - if:221 properties:222 compatible:223 contains:224 enum:225 - fsl,imx6q-pcie226 - fsl,imx6sx-pcie227 - fsl,imx6qp-pcie228 - fsl,imx7d-pcie229 - fsl,imx8mq-pcie230 - fsl,imx6q-pcie-ep231 - fsl,imx6sx-pcie-ep232 - fsl,imx6qp-pcie-ep233 - fsl,imx7d-pcie-ep234 - fsl,imx8mq-pcie-ep235 then:236 properties:237 resets:238 minItems: 3239 reset-names:240 items:241 - const: pciephy242 - const: apps243 - const: turnoff244 else:245 properties:246 resets:247 maxItems: 2248 reset-names:249 items:250 - const: apps251 - const: turnoff252 253additionalProperties: true254 255...256