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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/pci/fsl,imx6q-pcie-ep.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Freescale i.MX6 PCIe Endpoint controller8 9maintainers:10 - Lucas Stach <l.stach@pengutronix.de>11 - Richard Zhu <hongxing.zhu@nxp.com>12 13description: |+14 This PCIe controller is based on the Synopsys DesignWare PCIe IP and15 thus inherits all the common properties defined in snps,dw-pcie-ep.yaml.16 The controller instances are dual mode where in they can work either in17 Root Port mode or Endpoint mode but one at a time.18 19properties:20 compatible:21 enum:22 - fsl,imx8mm-pcie-ep23 - fsl,imx8mq-pcie-ep24 - fsl,imx8mp-pcie-ep25 - fsl,imx95-pcie-ep26 27 clocks:28 minItems: 329 items:30 - description: PCIe bridge clock.31 - description: PCIe bus clock.32 - description: PCIe PHY clock.33 - description: Additional required clock entry for imx6sx-pcie,34 imx6sx-pcie-ep, imx8mq-pcie, imx8mq-pcie-ep.35 36 clock-names:37 minItems: 338 maxItems: 439 40 interrupts:41 items:42 - description: builtin eDMA interrupter.43 44 interrupt-names:45 items:46 - const: dma47 48required:49 - compatible50 - reg51 - reg-names52 - interrupts53 - interrupt-names54 55allOf:56 - $ref: /schemas/pci/snps,dw-pcie-ep.yaml#57 - $ref: /schemas/pci/fsl,imx6q-pcie-common.yaml#58 - if:59 properties:60 compatible:61 enum:62 - fsl,imx8mm-pcie-ep63 - fsl,imx8mq-pcie-ep64 - fsl,imx8mp-pcie-ep65 then:66 properties:67 reg:68 minItems: 469 maxItems: 470 reg-names:71 items:72 - const: dbi73 - const: addr_space74 - const: dbi275 - const: atu76 77 - if:78 properties:79 compatible:80 enum:81 - fsl,imx95-pcie-ep82 then:83 properties:84 reg:85 minItems: 686 maxItems: 687 reg-names:88 items:89 - const: dbi90 - const: atu91 - const: dbi292 - const: app93 - const: dma94 - const: addr_space95 96 - if:97 properties:98 compatible:99 enum:100 - fsl,imx8mq-pcie-ep101 - fsl,imx95-pcie-ep102 then:103 properties:104 clocks:105 minItems: 4106 clock-names:107 items:108 - const: pcie109 - const: pcie_bus110 - const: pcie_phy111 - const: pcie_aux112 else:113 properties:114 clocks:115 maxItems: 3116 clock-names:117 items:118 - const: pcie119 - const: pcie_bus120 - const: pcie_aux121 122 123unevaluatedProperties: false124 125examples:126 - |127 #include <dt-bindings/clock/imx8mp-clock.h>128 #include <dt-bindings/power/imx8mp-power.h>129 #include <dt-bindings/reset/imx8mp-reset.h>130 #include <dt-bindings/interrupt-controller/arm-gic.h>131 132 pcie_ep: pcie-ep@33800000 {133 compatible = "fsl,imx8mp-pcie-ep";134 reg = <0x33800000 0x100000>,135 <0x18000000 0x8000000>,136 <0x33900000 0x100000>,137 <0x33b00000 0x100000>;138 reg-names = "dbi", "addr_space", "dbi2", "atu";139 clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,140 <&clk IMX8MP_CLK_HSIO_AXI>,141 <&clk IMX8MP_CLK_PCIE_ROOT>;142 clock-names = "pcie", "pcie_bus", "pcie_aux";143 assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>;144 assigned-clock-rates = <10000000>;145 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>;146 num-lanes = <1>;147 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; /* eDMA */148 interrupt-names = "dma";149 fsl,max-link-speed = <3>;150 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_PCIE>;151 resets = <&src IMX8MP_RESET_PCIE_CTRL_APPS_EN>,152 <&src IMX8MP_RESET_PCIE_CTRL_APPS_TURNOFF>;153 reset-names = "apps", "turnoff";154 phys = <&pcie_phy>;155 phy-names = "pcie-phy";156 num-ib-windows = <4>;157 num-ob-windows = <4>;158 };159