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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/pci/fsl,imx6q-pcie.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Freescale i.MX6 PCIe host controller8 9maintainers:10 - Lucas Stach <l.stach@pengutronix.de>11 - Richard Zhu <hongxing.zhu@nxp.com>12 13description: |+14 This PCIe host controller is based on the Synopsys DesignWare PCIe IP15 and thus inherits all the common properties defined in snps,dw-pcie.yaml.16 The controller instances are dual mode where in they can work either in17 Root Port mode or Endpoint mode but one at a time.18 19 See fsl,imx6q-pcie-ep.yaml for details on the Endpoint mode device tree20 bindings.21 22properties:23 compatible:24 enum:25 - fsl,imx6q-pcie26 - fsl,imx6sx-pcie27 - fsl,imx6qp-pcie28 - fsl,imx7d-pcie29 - fsl,imx8mq-pcie30 - fsl,imx8mm-pcie31 - fsl,imx8mp-pcie32 - fsl,imx95-pcie33 - fsl,imx8q-pcie34 35 clocks:36 minItems: 337 items:38 - description: PCIe bridge clock.39 - description: PCIe bus clock.40 - description: PCIe PHY clock.41 - description: Additional required clock entry for imx6sx-pcie,42 imx6sx-pcie-ep, imx8mq-pcie, imx8mq-pcie-ep.43 44 clock-names:45 minItems: 346 maxItems: 447 48 interrupts:49 items:50 - description: builtin MSI controller.51 52 interrupt-names:53 items:54 - const: msi55 56 reset-gpio:57 description: Should specify the GPIO for controlling the PCI bus device58 reset signal. It's not polarity aware and defaults to active-low reset59 sequence (L=reset state, H=operation state) (optional required).60 61 reset-gpio-active-high:62 description: If present then the reset sequence using the GPIO63 specified in the "reset-gpio" property is reversed (H=reset state,64 L=operation state) (optional required).65 type: boolean66 67required:68 - compatible69 - reg70 - reg-names71 - "#address-cells"72 - "#size-cells"73 - device_type74 - bus-range75 - ranges76 - interrupts77 - interrupt-names78 - "#interrupt-cells"79 - interrupt-map-mask80 - interrupt-map81 82allOf:83 - $ref: /schemas/pci/snps,dw-pcie.yaml#84 - $ref: /schemas/pci/fsl,imx6q-pcie-common.yaml#85 - if:86 properties:87 compatible:88 enum:89 - fsl,imx6q-pcie90 - fsl,imx6sx-pcie91 - fsl,imx6qp-pcie92 - fsl,imx7d-pcie93 - fsl,imx8mq-pcie94 - fsl,imx8mm-pcie95 - fsl,imx8mp-pcie96 then:97 properties:98 reg:99 maxItems: 2100 reg-names:101 items:102 - const: dbi103 - const: config104 105 - if:106 properties:107 compatible:108 enum:109 - fsl,imx95-pcie110 then:111 properties:112 reg:113 minItems: 4114 maxItems: 4115 reg-names:116 items:117 - const: dbi118 - const: config119 - const: atu120 - const: app121 122 - if:123 properties:124 compatible:125 enum:126 - fsl,imx6sx-pcie127 then:128 properties:129 clocks:130 minItems: 4131 clock-names:132 items:133 - const: pcie134 - const: pcie_bus135 - const: pcie_phy136 - const: pcie_inbound_axi137 138 - if:139 properties:140 compatible:141 enum:142 - fsl,imx8mq-pcie143 - fsl,imx95-pcie144 then:145 properties:146 clocks:147 minItems: 4148 clock-names:149 items:150 - const: pcie151 - const: pcie_bus152 - const: pcie_phy153 - const: pcie_aux154 155 - if:156 properties:157 compatible:158 enum:159 - fsl,imx6q-pcie160 - fsl,imx6qp-pcie161 - fsl,imx7d-pcie162 then:163 properties:164 clocks:165 maxItems: 3166 clock-names:167 items:168 - const: pcie169 - const: pcie_bus170 - const: pcie_phy171 172 - if:173 properties:174 compatible:175 enum:176 - fsl,imx8mm-pcie177 - fsl,imx8mp-pcie178 then:179 properties:180 clocks:181 maxItems: 3182 clock-names:183 items:184 - const: pcie185 - const: pcie_bus186 - const: pcie_aux187 188 - if:189 properties:190 compatible:191 enum:192 - fsl,imx8q-pcie193 then:194 properties:195 clocks:196 maxItems: 3197 clock-names:198 items:199 - const: dbi200 - const: mstr201 - const: slv202 203unevaluatedProperties: false204 205examples:206 - |207 #include <dt-bindings/clock/imx6qdl-clock.h>208 #include <dt-bindings/interrupt-controller/arm-gic.h>209 210 pcie: pcie@1ffc000 {211 compatible = "fsl,imx6q-pcie";212 reg = <0x01ffc000 0x04000>,213 <0x01f00000 0x80000>;214 reg-names = "dbi", "config";215 #address-cells = <3>;216 #size-cells = <2>;217 device_type = "pci";218 bus-range = <0x00 0xff>;219 ranges = <0x81000000 0 0 0x01f80000 0 0x00010000>,220 <0x82000000 0 0x01000000 0x01000000 0 0x00f00000>;221 num-lanes = <1>;222 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;223 interrupt-names = "msi";224 #interrupt-cells = <1>;225 interrupt-map-mask = <0 0 0 0x7>;226 interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,227 <0 0 0 2 &gpc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,228 <0 0 0 3 &gpc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,229 <0 0 0 4 &gpc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;230 clocks = <&clks IMX6QDL_CLK_PCIE_AXI>,231 <&clks IMX6QDL_CLK_LVDS1_GATE>,232 <&clks IMX6QDL_CLK_PCIE_REF_125M>;233 clock-names = "pcie", "pcie_bus", "pcie_phy";234 };235...236