118 lines · yaml
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/pci/intel-gw-pcie.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: PCIe RC controller on Intel Gateway SoCs8 9maintainers:10 - Rahul Tanwar <rtanwar@maxlinear.com>11 12select:13 properties:14 compatible:15 contains:16 const: intel,lgm-pcie17 required:18 - compatible19 20allOf:21 - $ref: /schemas/pci/snps,dw-pcie.yaml#22 23properties:24 compatible:25 items:26 - const: intel,lgm-pcie27 - const: snps,dw-pcie28 29 reg:30 items:31 - description: Controller control and status registers.32 - description: PCIe configuration registers.33 - description: Controller application registers.34 35 reg-names:36 items:37 - const: dbi38 - const: config39 - const: app40 41 ranges:42 maxItems: 143 44 resets:45 maxItems: 146 47 clocks:48 maxItems: 149 50 phys:51 maxItems: 152 53 phy-names:54 const: pcie55 56 reset-gpios:57 maxItems: 158 59 num-lanes:60 maximum: 261 62 max-link-speed:63 enum: [1, 2, 3, 4]64 default: 165 66 reset-assert-ms:67 description: |68 Delay after asserting reset to the PCIe device.69 maximum: 50070 default: 10071 72required:73 - compatible74 - reg75 - reg-names76 - ranges77 - resets78 - clocks79 - phys80 - phy-names81 - reset-gpios82 - '#interrupt-cells'83 - interrupt-map84 - interrupt-map-mask85 86unevaluatedProperties: false87 88examples:89 - |90 #include <dt-bindings/gpio/gpio.h>91 pcie10: pcie@d0e00000 {92 compatible = "intel,lgm-pcie", "snps,dw-pcie";93 device_type = "pci";94 #address-cells = <3>;95 #size-cells = <2>;96 reg = <0xd0e00000 0x1000>,97 <0xd2000000 0x800000>,98 <0xd0a41000 0x1000>;99 reg-names = "dbi", "config", "app";100 linux,pci-domain = <0>;101 max-link-speed = <4>;102 bus-range = <0x00 0x08>;103 #interrupt-cells = <1>;104 interrupt-map-mask = <0 0 0 0x7>;105 interrupt-map = <0 0 0 1 &ioapic1 27 1>,106 <0 0 0 2 &ioapic1 28 1>,107 <0 0 0 3 &ioapic1 29 1>,108 <0 0 0 4 &ioapic1 30 1>;109 ranges = <0x02000000 0 0xd4000000 0xd4000000 0 0x04000000>;110 resets = <&rcu0 0x50 0>;111 clocks = <&cgu0 120>;112 phys = <&cb0phy0>;113 phy-names = "pcie";114 reset-assert-ms = <500>;115 reset-gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;116 num-lanes = <2>;117 };118