301 lines · yaml
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/pci/mediatek-pcie-gen3.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Gen3 PCIe controller on MediaTek SoCs8 9maintainers:10 - Jianjun Wang <jianjun.wang@mediatek.com>11 12description: |+13 PCIe Gen3 MAC controller for MediaTek SoCs, it supports Gen3 speed14 and compatible with Gen2, Gen1 speed.15 16 This PCIe controller supports up to 256 MSI vectors, the MSI hardware17 block diagram is as follows:18 19 +-----+20 | GIC |21 +-----+22 ^23 |24 port->irq25 |26 +-+-+-+-+-+-+-+-+27 |0|1|2|3|4|5|6|7| (PCIe intc)28 +-+-+-+-+-+-+-+-+29 ^ ^ ^30 | | ... |31 +-------+ +------+ +-----------+32 | | |33 +-+-+---+--+--+ +-+-+---+--+--+ +-+-+---+--+--+34 |0|1|...|30|31| |0|1|...|30|31| |0|1|...|30|31| (MSI sets)35 +-+-+---+--+--+ +-+-+---+--+--+ +-+-+---+--+--+36 ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^37 | | | | | | | | | | | | (MSI vectors)38 | | | | | | | | | | | |39 40 (MSI SET0) (MSI SET1) ... (MSI SET7)41 42 With 256 MSI vectors supported, the MSI vectors are composed of 8 sets,43 each set has its own address for MSI message, and supports 32 MSI vectors44 to generate interrupt.45 46properties:47 compatible:48 oneOf:49 - items:50 - enum:51 - mediatek,mt7986-pcie52 - mediatek,mt8188-pcie53 - mediatek,mt8195-pcie54 - const: mediatek,mt8192-pcie55 - const: mediatek,mt8192-pcie56 - const: airoha,en7581-pcie57 58 reg:59 maxItems: 160 61 reg-names:62 items:63 - const: pcie-mac64 65 interrupts:66 maxItems: 167 68 ranges:69 minItems: 170 maxItems: 871 72 iommu-map:73 maxItems: 174 75 iommu-map-mask:76 const: 077 78 resets:79 minItems: 180 maxItems: 381 82 reset-names:83 minItems: 184 maxItems: 385 items:86 enum: [ phy, mac, phy-lane0, phy-lane1, phy-lane2 ]87 88 clocks:89 minItems: 190 maxItems: 691 92 clock-names:93 minItems: 194 maxItems: 695 96 assigned-clocks:97 maxItems: 198 99 assigned-clock-parents:100 maxItems: 1101 102 phys:103 maxItems: 1104 105 phy-names:106 items:107 - const: pcie-phy108 109 power-domains:110 maxItems: 1111 112 '#interrupt-cells':113 const: 1114 115 interrupt-controller:116 description: Interrupt controller node for handling legacy PCI interrupts.117 type: object118 properties:119 '#address-cells':120 const: 0121 '#interrupt-cells':122 const: 1123 interrupt-controller: true124 125 required:126 - '#address-cells'127 - '#interrupt-cells'128 - interrupt-controller129 130 additionalProperties: false131 132required:133 - compatible134 - reg135 - reg-names136 - interrupts137 - ranges138 - clocks139 - clock-names140 - '#interrupt-cells'141 - interrupt-controller142 143allOf:144 - $ref: /schemas/pci/pci-host-bridge.yaml#145 - if:146 properties:147 compatible:148 const: mediatek,mt8192-pcie149 then:150 properties:151 clocks:152 minItems: 4153 154 clock-names:155 items:156 - const: pl_250m157 - const: tl_26m158 - const: tl_96m159 - const: tl_32k160 - const: peri_26m161 - const: top_133m162 163 resets:164 minItems: 1165 maxItems: 2166 167 reset-names:168 minItems: 1169 maxItems: 2170 171 - if:172 properties:173 compatible:174 contains:175 enum:176 - mediatek,mt8188-pcie177 - mediatek,mt8195-pcie178 then:179 properties:180 clocks:181 minItems: 4182 183 clock-names:184 items:185 - const: pl_250m186 - const: tl_26m187 - const: tl_96m188 - const: tl_32k189 - const: peri_26m190 - const: peri_mem191 192 resets:193 minItems: 1194 maxItems: 2195 196 reset-names:197 minItems: 1198 maxItems: 2199 200 - if:201 properties:202 compatible:203 contains:204 enum:205 - mediatek,mt7986-pcie206 then:207 properties:208 clocks:209 minItems: 4210 211 clock-names:212 items:213 - const: pl_250m214 - const: tl_26m215 - const: peri_26m216 - const: top_133m217 218 resets:219 minItems: 1220 maxItems: 2221 222 reset-names:223 minItems: 1224 maxItems: 2225 226 - if:227 properties:228 compatible:229 const: airoha,en7581-pcie230 then:231 properties:232 clocks:233 maxItems: 1234 235 clock-names:236 items:237 - const: sys-ck238 239 resets:240 minItems: 3241 242 reset-names:243 items:244 - const: phy-lane0245 - const: phy-lane1246 - const: phy-lane2247 248unevaluatedProperties: false249 250examples:251 - |252 #include <dt-bindings/interrupt-controller/arm-gic.h>253 #include <dt-bindings/interrupt-controller/irq.h>254 255 bus {256 #address-cells = <2>;257 #size-cells = <2>;258 259 pcie: pcie@11230000 {260 compatible = "mediatek,mt8192-pcie";261 device_type = "pci";262 #address-cells = <3>;263 #size-cells = <2>;264 reg = <0x00 0x11230000 0x00 0x4000>;265 reg-names = "pcie-mac";266 interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH 0>;267 bus-range = <0x00 0xff>;268 ranges = <0x82000000 0x00 0x12000000 0x00269 0x12000000 0x00 0x1000000>;270 clocks = <&infracfg 44>,271 <&infracfg 40>,272 <&infracfg 43>,273 <&infracfg 97>,274 <&infracfg 99>,275 <&infracfg 111>;276 clock-names = "pl_250m", "tl_26m", "tl_96m",277 "tl_32k", "peri_26m", "top_133m";278 assigned-clocks = <&topckgen 50>;279 assigned-clock-parents = <&topckgen 91>;280 281 phys = <&pciephy>;282 phy-names = "pcie-phy";283 284 resets = <&infracfg_rst 2>,285 <&infracfg_rst 3>;286 reset-names = "phy", "mac";287 288 #interrupt-cells = <1>;289 interrupt-map-mask = <0 0 0 0x7>;290 interrupt-map = <0 0 0 1 &pcie_intc 0>,291 <0 0 0 2 &pcie_intc 1>,292 <0 0 0 3 &pcie_intc 2>,293 <0 0 0 4 &pcie_intc 3>;294 pcie_intc: interrupt-controller {295 #address-cells = <0>;296 #interrupt-cells = <1>;297 interrupt-controller;298 };299 };300 };301