285 lines · yaml
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/pci/qcom,pcie-ep.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Qualcomm PCIe Endpoint Controller8 9maintainers:10 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>11 12properties:13 compatible:14 oneOf:15 - enum:16 - qcom,sa8775p-pcie-ep17 - qcom,sdx55-pcie-ep18 - qcom,sm8450-pcie-ep19 - items:20 - const: qcom,sdx65-pcie-ep21 - const: qcom,sdx55-pcie-ep22 23 reg:24 minItems: 625 items:26 - description: Qualcomm-specific PARF configuration registers27 - description: DesignWare PCIe registers28 - description: External local bus interface registers29 - description: Address Translation Unit (ATU) registers30 - description: Memory region used to map remote RC address space31 - description: BAR memory region32 - description: DMA register space33 34 reg-names:35 minItems: 636 items:37 - const: parf38 - const: dbi39 - const: elbi40 - const: atu41 - const: addr_space42 - const: mmio43 - const: dma44 45 clocks:46 minItems: 547 maxItems: 848 49 clock-names:50 minItems: 551 maxItems: 852 53 qcom,perst-regs:54 description: Reference to a syscon representing TCSR followed by the two55 offsets within syscon for Perst enable and Perst separation56 enable registers57 $ref: /schemas/types.yaml#/definitions/phandle-array58 items:59 - items:60 - description: Syscon to TCSR system registers61 - description: Perst enable offset62 - description: Perst separation enable offset63 64 interrupts:65 minItems: 266 items:67 - description: PCIe Global interrupt68 - description: PCIe Doorbell interrupt69 - description: DMA interrupt70 71 interrupt-names:72 minItems: 273 items:74 - const: global75 - const: doorbell76 - const: dma77 78 reset-gpios:79 description: GPIO used as PERST# input signal80 maxItems: 181 82 wake-gpios:83 description: GPIO used as WAKE# output signal84 maxItems: 185 86 interconnects:87 maxItems: 288 89 interconnect-names:90 items:91 - const: pcie-mem92 - const: cpu-pcie93 94 resets:95 maxItems: 196 97 reset-names:98 const: core99 100 power-domains:101 maxItems: 1102 103 phys:104 maxItems: 1105 106 phy-names:107 const: pciephy108 109 num-lanes:110 default: 2111 112required:113 - compatible114 - reg115 - reg-names116 - clocks117 - clock-names118 - interrupts119 - interrupt-names120 - reset-gpios121 - interconnects122 - interconnect-names123 - resets124 - reset-names125 - power-domains126 127allOf:128 - $ref: pci-ep.yaml#129 - if:130 properties:131 compatible:132 contains:133 enum:134 - qcom,sdx55-pcie-ep135 then:136 properties:137 reg:138 maxItems: 6139 reg-names:140 maxItems: 6141 clocks:142 items:143 - description: PCIe Auxiliary clock144 - description: PCIe CFG AHB clock145 - description: PCIe Master AXI clock146 - description: PCIe Slave AXI clock147 - description: PCIe Slave Q2A AXI clock148 - description: PCIe Sleep clock149 - description: PCIe Reference clock150 clock-names:151 items:152 - const: aux153 - const: cfg154 - const: bus_master155 - const: bus_slave156 - const: slave_q2a157 - const: sleep158 - const: ref159 interrupts:160 maxItems: 2161 interrupt-names:162 maxItems: 2163 164 - if:165 properties:166 compatible:167 contains:168 enum:169 - qcom,sm8450-pcie-ep170 then:171 properties:172 reg:173 maxItems: 6174 reg-names:175 maxItems: 6176 clocks:177 items:178 - description: PCIe Auxiliary clock179 - description: PCIe CFG AHB clock180 - description: PCIe Master AXI clock181 - description: PCIe Slave AXI clock182 - description: PCIe Slave Q2A AXI clock183 - description: PCIe Reference clock184 - description: PCIe DDRSS SF TBU clock185 - description: PCIe AGGRE NOC AXI clock186 clock-names:187 items:188 - const: aux189 - const: cfg190 - const: bus_master191 - const: bus_slave192 - const: slave_q2a193 - const: ref194 - const: ddrss_sf_tbu195 - const: aggre_noc_axi196 interrupts:197 maxItems: 2198 interrupt-names:199 maxItems: 2200 201 - if:202 properties:203 compatible:204 contains:205 enum:206 - qcom,sa8775p-pcie-ep207 then:208 properties:209 reg:210 minItems: 7211 maxItems: 7212 reg-names:213 minItems: 7214 maxItems: 7215 clocks:216 items:217 - description: PCIe Auxiliary clock218 - description: PCIe CFG AHB clock219 - description: PCIe Master AXI clock220 - description: PCIe Slave AXI clock221 - description: PCIe Slave Q2A AXI clock222 clock-names:223 items:224 - const: aux225 - const: cfg226 - const: bus_master227 - const: bus_slave228 - const: slave_q2a229 interrupts:230 minItems: 3231 maxItems: 3232 interrupt-names:233 minItems: 3234 maxItems: 3235 236unevaluatedProperties: false237 238examples:239 - |240 #include <dt-bindings/clock/qcom,gcc-sdx55.h>241 #include <dt-bindings/gpio/gpio.h>242 #include <dt-bindings/interconnect/qcom,sdx55.h>243 #include <dt-bindings/interrupt-controller/arm-gic.h>244 245 pcie_ep: pcie-ep@1c00000 {246 compatible = "qcom,sdx55-pcie-ep";247 reg = <0x01c00000 0x3000>,248 <0x40000000 0xf1d>,249 <0x40000f20 0xc8>,250 <0x40001000 0x1000>,251 <0x40002000 0x1000>,252 <0x01c03000 0x3000>;253 reg-names = "parf", "dbi", "elbi", "atu", "addr_space",254 "mmio";255 256 clocks = <&gcc GCC_PCIE_AUX_CLK>,257 <&gcc GCC_PCIE_CFG_AHB_CLK>,258 <&gcc GCC_PCIE_MSTR_AXI_CLK>,259 <&gcc GCC_PCIE_SLV_AXI_CLK>,260 <&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>,261 <&gcc GCC_PCIE_SLEEP_CLK>,262 <&gcc GCC_PCIE_0_CLKREF_CLK>;263 clock-names = "aux", "cfg", "bus_master", "bus_slave",264 "slave_q2a", "sleep", "ref";265 266 qcom,perst-regs = <&tcsr 0xb258 0xb270>;267 268 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,269 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;270 interrupt-names = "global", "doorbell";271 interconnects = <&system_noc MASTER_PCIE &mc_virt SLAVE_EBI_CH0>,272 <&mem_noc MASTER_AMPSS_M0 &system_noc SLAVE_PCIE_0>;273 interconnect-names = "pcie-mem", "cpu-pcie";274 reset-gpios = <&tlmm 57 GPIO_ACTIVE_LOW>;275 wake-gpios = <&tlmm 53 GPIO_ACTIVE_LOW>;276 resets = <&gcc GCC_PCIE_BCR>;277 reset-names = "core";278 power-domains = <&gcc PCIE_GDSC>;279 phys = <&pcie0_lane>;280 phy-names = "pciephy";281 max-link-speed = <3>;282 num-lanes = <2>;283 linux,pci-domain = <0>;284 };285