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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/pci/qcom,pcie-sa8775p.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Qualcomm SA8775p PCI Express Root Complex8 9maintainers:10 - Bjorn Andersson <andersson@kernel.org>11 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>12 13description:14 Qualcomm SA8775p SoC PCIe root complex controller is based on the Synopsys15 DesignWare PCIe IP.16 17properties:18 compatible:19 const: qcom,pcie-sa8775p20 21 reg:22 minItems: 623 maxItems: 624 25 reg-names:26 items:27 - const: parf # Qualcomm specific registers28 - const: dbi # DesignWare PCIe registers29 - const: elbi # External local bus interface registers30 - const: atu # ATU address space31 - const: config # PCIe configuration space32 - const: mhi # MHI registers33 34 clocks:35 minItems: 536 maxItems: 537 38 clock-names:39 items:40 - const: aux # Auxiliary clock41 - const: cfg # Configuration clock42 - const: bus_master # Master AXI clock43 - const: bus_slave # Slave AXI clock44 - const: slave_q2a # Slave Q2A clock45 46 interrupts:47 minItems: 848 maxItems: 849 50 interrupt-names:51 items:52 - const: msi053 - const: msi154 - const: msi255 - const: msi356 - const: msi457 - const: msi558 - const: msi659 - const: msi760 61 resets:62 maxItems: 163 64 reset-names:65 items:66 - const: pci67 68required:69 - interconnects70 - interconnect-names71 72allOf:73 - $ref: qcom,pcie-common.yaml#74 75unevaluatedProperties: false76 77examples:78 - |79 #include <dt-bindings/clock/qcom,sa8775p-gcc.h>80 #include <dt-bindings/clock/qcom,rpmh.h>81 #include <dt-bindings/gpio/gpio.h>82 #include <dt-bindings/interrupt-controller/arm-gic.h>83 #include <dt-bindings/interconnect/qcom,sa8775p-rpmh.h>84 85 soc {86 #address-cells = <2>;87 #size-cells = <2>;88 89 pcie@1c00000 {90 compatible = "qcom,pcie-sa8775p";91 reg = <0x0 0x01c00000 0x0 0x3000>,92 <0x0 0x40000000 0x0 0xf20>,93 <0x0 0x40000f20 0x0 0xa8>,94 <0x0 0x40001000 0x0 0x4000>,95 <0x0 0x40100000 0x0 0x100000>,96 <0x0 0x01c03000 0x0 0x1000>;97 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";98 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,99 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;100 101 bus-range = <0x00 0xff>;102 device_type = "pci";103 linux,pci-domain = <0>;104 num-lanes = <2>;105 106 #address-cells = <3>;107 #size-cells = <2>;108 109 assigned-clocks = <&gcc GCC_PCIE_0_AUX_CLK>;110 assigned-clock-rates = <19200000>;111 112 clocks = <&gcc GCC_PCIE_0_AUX_CLK>,113 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,114 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,115 <&gcc GCC_PCIE_0_SLV_AXI_CLK>,116 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>;117 clock-names = "aux",118 "cfg",119 "bus_master",120 "bus_slave",121 "slave_q2a";122 123 dma-coherent;124 125 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,126 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,127 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,128 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,129 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,130 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,131 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,132 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;133 interrupt-names = "msi0",134 "msi1",135 "msi2",136 "msi3",137 "msi4",138 "msi5",139 "msi6",140 "msi7";141 #interrupt-cells = <1>;142 interrupt-map-mask = <0 0 0 0x7>;143 interrupt-map = <0 0 0 1 &intc GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>,144 <0 0 0 2 &intc GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>,145 <0 0 0 3 &intc GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>,146 <0 0 0 4 &intc GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>;147 148 interconnects = <&pcie_anoc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>,149 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_0 0>;150 interconnect-names = "pcie-mem", "cpu-pcie";151 152 iommu-map = <0x0 &pcie_smmu 0x0000 0x1>,153 <0x100 &pcie_smmu 0x0001 0x1>;154 155 phys = <&pcie0_phy>;156 phy-names = "pciephy";157 158 power-domains = <&gcc PCIE_0_GDSC>;159 160 resets = <&gcc GCC_PCIE_0_BCR>;161 reset-names = "pci";162 163 perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;164 wake-gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;165 };166 };167