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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/pci/qcom,pcie-sc8180x.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Qualcomm SC8180x PCI Express Root Complex8 9maintainers:10 - Bjorn Andersson <andersson@kernel.org>11 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>12 13description:14 Qualcomm SC8180x SoC PCIe root complex controller is based on the Synopsys15 DesignWare PCIe IP.16 17properties:18 compatible:19 const: qcom,pcie-sc8180x20 21 reg:22 minItems: 523 maxItems: 624 25 reg-names:26 minItems: 527 items:28 - const: parf # Qualcomm specific registers29 - const: dbi # DesignWare PCIe registers30 - const: elbi # External local bus interface registers31 - const: atu # ATU address space32 - const: config # PCIe configuration space33 - const: mhi # MHI registers34 35 clocks:36 minItems: 837 maxItems: 838 39 clock-names:40 items:41 - const: pipe # PIPE clock42 - const: aux # Auxiliary clock43 - const: cfg # Configuration clock44 - const: bus_master # Master AXI clock45 - const: bus_slave # Slave AXI clock46 - const: slave_q2a # Slave Q2A clock47 - const: ref # REFERENCE clock48 - const: tbu # PCIe TBU clock49 50 interrupts:51 minItems: 852 maxItems: 853 54 interrupt-names:55 items:56 - const: msi057 - const: msi158 - const: msi259 - const: msi360 - const: msi461 - const: msi562 - const: msi663 - const: msi764 65 resets:66 maxItems: 167 68 reset-names:69 items:70 - const: pci71 72allOf:73 - $ref: qcom,pcie-common.yaml#74 75unevaluatedProperties: false76 77examples:78 - |79 #include <dt-bindings/clock/qcom,gcc-sc8180x.h>80 #include <dt-bindings/interconnect/qcom,sc8180x.h>81 #include <dt-bindings/interrupt-controller/arm-gic.h>82 83 soc {84 #address-cells = <2>;85 #size-cells = <2>;86 87 pcie@1c00000 {88 compatible = "qcom,pcie-sc8180x";89 reg = <0 0x01c00000 0 0x3000>,90 <0 0x60000000 0 0xf1d>,91 <0 0x60000f20 0 0xa8>,92 <0 0x60001000 0 0x1000>,93 <0 0x60100000 0 0x100000>;94 reg-names = "parf",95 "dbi",96 "elbi",97 "atu",98 "config";99 ranges = <0x01000000 0x0 0x60200000 0x0 0x60200000 0x0 0x100000>,100 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;101 102 bus-range = <0x00 0xff>;103 device_type = "pci";104 linux,pci-domain = <0>;105 num-lanes = <2>;106 107 #address-cells = <3>;108 #size-cells = <2>;109 110 assigned-clocks = <&gcc GCC_PCIE_0_AUX_CLK>;111 assigned-clock-rates = <19200000>;112 113 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,114 <&gcc GCC_PCIE_0_AUX_CLK>,115 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,116 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,117 <&gcc GCC_PCIE_0_SLV_AXI_CLK>,118 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,119 <&gcc GCC_PCIE_0_CLKREF_CLK>,120 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;121 clock-names = "pipe",122 "aux",123 "cfg",124 "bus_master",125 "bus_slave",126 "slave_q2a",127 "ref",128 "tbu";129 130 dma-coherent;131 132 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,133 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,134 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,135 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,136 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,137 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,138 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,139 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;140 interrupt-names = "msi0",141 "msi1",142 "msi2",143 "msi3",144 "msi4",145 "msi5",146 "msi6",147 "msi7";148 #interrupt-cells = <1>;149 interrupt-map-mask = <0 0 0 0x7>;150 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */151 <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */152 <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */153 <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */154 155 interconnects = <&aggre2_noc MASTER_PCIE 0 &mc_virt SLAVE_EBI_CH0 0>,156 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_0 0>;157 interconnect-names = "pcie-mem", "cpu-pcie";158 159 iommu-map = <0x0 &apps_smmu 0x1d80 0x1>,160 <0x100 &apps_smmu 0x1d81 0x1>;161 162 phys = <&pcie0_phy>;163 phy-names = "pciephy";164 165 power-domains = <&gcc PCIE_0_GDSC>;166 167 resets = <&gcc GCC_PCIE_0_BCR>;168 reset-names = "pci";169 };170 };171