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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/pci/qcom,pcie-sc8280xp.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Qualcomm SC8280XP PCI Express Root Complex8 9maintainers:10 - Bjorn Andersson <andersson@kernel.org>11 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>12 13description:14 Qualcomm SC8280XP SoC PCIe root complex controller is based on the Synopsys15 DesignWare PCIe IP.16 17properties:18 compatible:19 enum:20 - qcom,pcie-sa8540p21 - qcom,pcie-sc8280xp22 23 reg:24 minItems: 525 maxItems: 626 27 reg-names:28 minItems: 529 items:30 - const: parf # Qualcomm specific registers31 - const: dbi # DesignWare PCIe registers32 - const: elbi # External local bus interface registers33 - const: atu # ATU address space34 - const: config # PCIe configuration space35 - const: mhi # MHI registers36 37 clocks:38 minItems: 839 maxItems: 940 41 clock-names:42 minItems: 843 items:44 - const: aux # Auxiliary clock45 - const: cfg # Configuration clock46 - const: bus_master # Master AXI clock47 - const: bus_slave # Slave AXI clock48 - const: slave_q2a # Slave Q2A clock49 - const: ddrss_sf_tbu # PCIe SF TBU clock50 - const: noc_aggr_4 # NoC aggregate 4 clock51 - const: noc_aggr_south_sf # NoC aggregate South SF clock52 - const: cnoc_qx # Configuration NoC QX clock53 54 resets:55 maxItems: 156 57 reset-names:58 items:59 - const: pci60 61required:62 - interconnects63 - interconnect-names64 65allOf:66 - $ref: qcom,pcie-common.yaml#67 - if:68 properties:69 compatible:70 contains:71 enum:72 - qcom,pcie-sc8280xp73 then:74 properties:75 interrupts:76 minItems: 477 maxItems: 478 interrupt-names:79 items:80 - const: msi081 - const: msi182 - const: msi283 - const: msi384 else:85 properties:86 interrupts:87 maxItems: 188 interrupt-names:89 items:90 - const: msi91 92unevaluatedProperties: false93 94examples:95 - |96 #include <dt-bindings/clock/qcom,gcc-sc8280xp.h>97 #include <dt-bindings/gpio/gpio.h>98 #include <dt-bindings/interconnect/qcom,sc8280xp.h>99 #include <dt-bindings/interrupt-controller/arm-gic.h>100 101 soc {102 #address-cells = <2>;103 #size-cells = <2>;104 105 pcie@1c20000 {106 compatible = "qcom,pcie-sc8280xp";107 reg = <0x0 0x01c20000 0x0 0x3000>,108 <0x0 0x3c000000 0x0 0xf1d>,109 <0x0 0x3c000f20 0x0 0xa8>,110 <0x0 0x3c001000 0x0 0x1000>,111 <0x0 0x3c100000 0x0 0x100000>,112 <0x0 0x01c23000 0x0 0x1000>;113 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";114 ranges = <0x01000000 0x0 0x00000000 0x0 0x3c200000 0x0 0x100000>,115 <0x02000000 0x0 0x3c300000 0x0 0x3c300000 0x0 0x1d00000>;116 117 bus-range = <0x00 0xff>;118 device_type = "pci";119 linux,pci-domain = <2>;120 num-lanes = <4>;121 122 #address-cells = <3>;123 #size-cells = <2>;124 125 assigned-clocks = <&gcc GCC_PCIE_2A_AUX_CLK>;126 assigned-clock-rates = <19200000>;127 clocks = <&gcc GCC_PCIE_2A_AUX_CLK>,128 <&gcc GCC_PCIE_2A_CFG_AHB_CLK>,129 <&gcc GCC_PCIE_2A_MSTR_AXI_CLK>,130 <&gcc GCC_PCIE_2A_SLV_AXI_CLK>,131 <&gcc GCC_PCIE_2A_SLV_Q2A_AXI_CLK>,132 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,133 <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>,134 <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>;135 clock-names = "aux",136 "cfg",137 "bus_master",138 "bus_slave",139 "slave_q2a",140 "ddrss_sf_tbu",141 "noc_aggr_4",142 "noc_aggr_south_sf";143 144 dma-coherent;145 146 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,147 <GIC_SPI 523 IRQ_TYPE_LEVEL_HIGH>,148 <GIC_SPI 524 IRQ_TYPE_LEVEL_HIGH>,149 <GIC_SPI 525 IRQ_TYPE_LEVEL_HIGH>;150 interrupt-names = "msi0", "msi1", "msi2", "msi3";151 #interrupt-cells = <1>;152 interrupt-map-mask = <0 0 0 0x7>;153 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>,154 <0 0 0 2 &intc 0 0 GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>,155 <0 0 0 3 &intc 0 0 GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH>,156 <0 0 0 4 &intc 0 0 GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>;157 158 interconnects = <&aggre2_noc MASTER_PCIE_2A 0 &mc_virt SLAVE_EBI1 0>,159 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_2A 0>;160 interconnect-names = "pcie-mem", "cpu-pcie";161 162 phys = <&pcie2a_phy>;163 phy-names = "pciephy";164 165 pinctrl-0 = <&pcie2a_default>;166 pinctrl-names = "default";167 168 power-domains = <&gcc PCIE_2A_GDSC>;169 170 resets = <&gcc GCC_PCIE_2A_BCR>;171 reset-names = "pci";172 173 perst-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>;174 wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>;175 vddpe-3v3-supply = <&vreg_nvme>;176 };177 };178