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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/pci/qcom,pcie-sm8250.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Qualcomm SM8250 PCI Express Root Complex8 9maintainers:10 - Bjorn Andersson <andersson@kernel.org>11 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>12 13description:14 Qualcomm SM8250 SoC PCIe root complex controller is based on the Synopsys15 DesignWare PCIe IP.16 17properties:18 compatible:19 const: qcom,pcie-sm825020 21 reg:22 minItems: 523 maxItems: 624 25 reg-names:26 minItems: 527 items:28 - const: parf # Qualcomm specific registers29 - const: dbi # DesignWare PCIe registers30 - const: elbi # External local bus interface registers31 - const: atu # ATU address space32 - const: config # PCIe configuration space33 - const: mhi # MHI registers34 35 clocks:36 minItems: 837 maxItems: 938 39 clock-names:40 # Unfortunately the "optional" ref clock is used in the middle of the list41 oneOf:42 - items:43 - const: pipe # PIPE clock44 - const: aux # Auxiliary clock45 - const: cfg # Configuration clock46 - const: bus_master # Master AXI clock47 - const: bus_slave # Slave AXI clock48 - const: slave_q2a # Slave Q2A clock49 - const: ref # REFERENCE clock50 - const: tbu # PCIe TBU clock51 - const: ddrss_sf_tbu # PCIe SF TBU clock52 - items:53 - const: pipe # PIPE clock54 - const: aux # Auxiliary clock55 - const: cfg # Configuration clock56 - const: bus_master # Master AXI clock57 - const: bus_slave # Slave AXI clock58 - const: slave_q2a # Slave Q2A clock59 - const: tbu # PCIe TBU clock60 - const: ddrss_sf_tbu # PCIe SF TBU clock61 62 interrupts:63 minItems: 864 maxItems: 865 66 interrupt-names:67 items:68 - const: msi069 - const: msi170 - const: msi271 - const: msi372 - const: msi473 - const: msi574 - const: msi675 - const: msi776 77 resets:78 maxItems: 179 80 reset-names:81 items:82 - const: pci83 84allOf:85 - $ref: qcom,pcie-common.yaml#86 87unevaluatedProperties: false88 89examples:90 - |91 #include <dt-bindings/clock/qcom,gcc-sm8250.h>92 #include <dt-bindings/gpio/gpio.h>93 #include <dt-bindings/interconnect/qcom,sm8250.h>94 #include <dt-bindings/interrupt-controller/arm-gic.h>95 96 soc {97 #address-cells = <2>;98 #size-cells = <2>;99 100 pcie@1c00000 {101 compatible = "qcom,pcie-sm8250";102 reg = <0 0x01c00000 0 0x3000>,103 <0 0x60000000 0 0xf1d>,104 <0 0x60000f20 0 0xa8>,105 <0 0x60001000 0 0x1000>,106 <0 0x60100000 0 0x100000>,107 <0 0x01c03000 0 0x1000>;108 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";109 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,110 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;111 112 bus-range = <0x00 0xff>;113 device_type = "pci";114 linux,pci-domain = <0>;115 num-lanes = <1>;116 117 #address-cells = <3>;118 #size-cells = <2>;119 120 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,121 <&gcc GCC_PCIE_0_AUX_CLK>,122 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,123 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,124 <&gcc GCC_PCIE_0_SLV_AXI_CLK>,125 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,126 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,127 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>;128 clock-names = "pipe",129 "aux",130 "cfg",131 "bus_master",132 "bus_slave",133 "slave_q2a",134 "tbu",135 "ddrss_sf_tbu";136 137 dma-coherent;138 139 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,140 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,141 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,142 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,143 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,144 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,145 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,146 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;147 interrupt-names = "msi0", "msi1", "msi2", "msi3",148 "msi4", "msi5", "msi6", "msi7";149 #interrupt-cells = <1>;150 interrupt-map-mask = <0 0 0 0x7>;151 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */152 <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */153 <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */154 <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */155 156 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,157 <0x100 &apps_smmu 0x1c01 0x1>;158 159 phys = <&pcie0_phy>;160 phy-names = "pciephy";161 162 pinctrl-0 = <&pcie0_default_state>;163 pinctrl-names = "default";164 165 power-domains = <&gcc PCIE_0_GDSC>;166 167 resets = <&gcc GCC_PCIE_0_BCR>;168 reset-names = "pci";169 170 perst-gpios = <&tlmm 79 GPIO_ACTIVE_LOW>;171 wake-gpios = <&tlmm 81 GPIO_ACTIVE_HIGH>;172 };173 };174