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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/pci/qcom,pcie-sm8350.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Qualcomm SM8350 PCI Express Root Complex8 9maintainers:10 - Bjorn Andersson <andersson@kernel.org>11 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>12 13description:14 Qualcomm SM8350 SoC PCIe root complex controller is based on the Synopsys15 DesignWare PCIe IP.16 17properties:18 compatible:19 const: qcom,pcie-sm835020 21 reg:22 minItems: 523 maxItems: 624 25 reg-names:26 minItems: 527 items:28 - const: parf # Qualcomm specific registers29 - const: dbi # DesignWare PCIe registers30 - const: elbi # External local bus interface registers31 - const: atu # ATU address space32 - const: config # PCIe configuration space33 - const: mhi # MHI registers34 35 clocks:36 minItems: 837 maxItems: 938 39 clock-names:40 minItems: 841 items:42 - const: aux # Auxiliary clock43 - const: cfg # Configuration clock44 - const: bus_master # Master AXI clock45 - const: bus_slave # Slave AXI clock46 - const: slave_q2a # Slave Q2A clock47 - const: tbu # PCIe TBU clock48 - const: ddrss_sf_tbu # PCIe SF TBU clock49 - const: aggre1 # Aggre NoC PCIe1 AXI clock50 - const: aggre0 # Aggre NoC PCIe0 AXI clock51 52 interrupts:53 minItems: 854 maxItems: 855 56 interrupt-names:57 items:58 - const: msi059 - const: msi160 - const: msi261 - const: msi362 - const: msi463 - const: msi564 - const: msi665 - const: msi766 67 resets:68 maxItems: 169 70 reset-names:71 items:72 - const: pci73 74allOf:75 - $ref: qcom,pcie-common.yaml#76 77unevaluatedProperties: false78 79examples:80 - |81 #include <dt-bindings/clock/qcom,gcc-sm8350.h>82 #include <dt-bindings/gpio/gpio.h>83 #include <dt-bindings/interconnect/qcom,sm8350.h>84 #include <dt-bindings/interrupt-controller/arm-gic.h>85 86 soc {87 #address-cells = <2>;88 #size-cells = <2>;89 90 pcie@1c00000 {91 compatible = "qcom,pcie-sm8350";92 reg = <0 0x01c00000 0 0x3000>,93 <0 0x60000000 0 0xf1d>,94 <0 0x60000f20 0 0xa8>,95 <0 0x60001000 0 0x1000>,96 <0 0x60100000 0 0x100000>;97 reg-names = "parf", "dbi", "elbi", "atu", "config";98 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,99 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;100 101 bus-range = <0x00 0xff>;102 device_type = "pci";103 linux,pci-domain = <0>;104 num-lanes = <1>;105 106 #address-cells = <3>;107 #size-cells = <2>;108 109 clocks = <&gcc GCC_PCIE_0_AUX_CLK>,110 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,111 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,112 <&gcc GCC_PCIE_0_SLV_AXI_CLK>,113 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,114 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,115 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,116 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>,117 <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>;118 clock-names = "aux",119 "cfg",120 "bus_master",121 "bus_slave",122 "slave_q2a",123 "tbu",124 "ddrss_sf_tbu",125 "aggre1",126 "aggre0";127 128 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,129 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,130 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,131 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,132 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,133 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,134 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,135 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;136 interrupt-names = "msi0", "msi1", "msi2", "msi3",137 "msi4", "msi5", "msi6", "msi7";138 #interrupt-cells = <1>;139 interrupt-map-mask = <0 0 0 0x7>;140 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */141 <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */142 <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */143 <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */144 145 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,146 <0x100 &apps_smmu 0x1c01 0x1>;147 148 phys = <&pcie0_phy>;149 phy-names = "pciephy";150 151 pinctrl-0 = <&pcie0_default_state>;152 pinctrl-names = "default";153 154 power-domains = <&gcc PCIE_0_GDSC>;155 156 resets = <&gcc GCC_PCIE_0_BCR>;157 reset-names = "pci";158 159 perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;160 wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;161 };162 };163