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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2# Copyright (C) 2022-2023 Renesas Electronics Corp.3%YAML 1.24---5$id: http://devicetree.org/schemas/pci/rcar-gen4-pci-ep.yaml#6$schema: http://devicetree.org/meta-schemas/core.yaml#7 8title: Renesas R-Car Gen4 PCIe Endpoint9 10maintainers:11 - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>12 13allOf:14 - $ref: snps,dw-pcie-ep.yaml#15 16properties:17 compatible:18 items:19 - enum:20 - renesas,r8a779f0-pcie-ep # R-Car S4-821 - renesas,r8a779g0-pcie-ep # R-Car V4H22 - renesas,r8a779h0-pcie-ep # R-Car V4M23 - const: renesas,rcar-gen4-pcie-ep # R-Car Gen424 25 reg:26 maxItems: 727 28 reg-names:29 items:30 - const: dbi31 - const: dbi232 - const: atu33 - const: dma34 - const: app35 - const: phy36 - const: addr_space37 38 interrupts:39 maxItems: 340 41 interrupt-names:42 items:43 - const: dma44 - const: sft_ce45 - const: app46 47 clocks:48 maxItems: 249 50 clock-names:51 items:52 - const: core53 - const: ref54 55 power-domains:56 maxItems: 157 58 resets:59 maxItems: 160 61 reset-names:62 items:63 - const: pwr64 65 max-link-speed:66 maximum: 467 68 num-lanes:69 maximum: 470 71 max-functions:72 maximum: 273 74required:75 - compatible76 - reg77 - reg-names78 - interrupts79 - interrupt-names80 - clocks81 - clock-names82 - power-domains83 - resets84 - reset-names85 86unevaluatedProperties: false87 88examples:89 - |90 #include <dt-bindings/clock/r8a779f0-cpg-mssr.h>91 #include <dt-bindings/interrupt-controller/arm-gic.h>92 #include <dt-bindings/power/r8a779f0-sysc.h>93 94 soc {95 #address-cells = <2>;96 #size-cells = <2>;97 98 pcie0_ep: pcie-ep@e65d0000 {99 compatible = "renesas,r8a779f0-pcie-ep", "renesas,rcar-gen4-pcie-ep";100 reg = <0 0xe65d0000 0 0x2000>, <0 0xe65d2000 0 0x1000>,101 <0 0xe65d3000 0 0x2000>, <0 0xe65d5000 0 0x1200>,102 <0 0xe65d6200 0 0x0e00>, <0 0xe65d7000 0 0x0400>,103 <0 0xfe000000 0 0x400000>;104 reg-names = "dbi", "dbi2", "atu", "dma", "app", "phy", "addr_space";105 interrupts = <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,106 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,107 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>;108 interrupt-names = "dma", "sft_ce", "app";109 clocks = <&cpg CPG_MOD 624>, <&pcie0_clkref>;110 clock-names = "core", "ref";111 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;112 resets = <&cpg 624>;113 reset-names = "pwr";114 max-link-speed = <4>;115 num-lanes = <2>;116 max-functions = /bits/ 8 <2>;117 };118 };119