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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/pci/rockchip-dw-pcie.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: DesignWare based PCIe Root Complex controller on Rockchip SoCs8 9maintainers:10 - Shawn Lin <shawn.lin@rock-chips.com>11 - Simon Xue <xxm@rock-chips.com>12 - Heiko Stuebner <heiko@sntech.de>13 14description: |+15 RK3568 SoC PCIe Root Complex controller is based on the Synopsys DesignWare16 PCIe IP and thus inherits all the common properties defined in17 snps,dw-pcie.yaml.18 19allOf:20 - $ref: /schemas/pci/snps,dw-pcie.yaml#21 - $ref: /schemas/pci/rockchip-dw-pcie-common.yaml#22 23properties:24 compatible:25 oneOf:26 - const: rockchip,rk3568-pcie27 - items:28 - enum:29 - rockchip,rk3588-pcie30 - const: rockchip,rk3568-pcie31 32 reg:33 items:34 - description: Data Bus Interface (DBI) registers35 - description: Rockchip designed configuration registers36 - description: Config registers37 38 reg-names:39 items:40 - const: dbi41 - const: apb42 - const: config43 44 legacy-interrupt-controller:45 description: Interrupt controller node for handling legacy PCI interrupts.46 type: object47 additionalProperties: false48 properties:49 "#address-cells":50 const: 051 52 "#interrupt-cells":53 const: 154 55 interrupt-controller: true56 57 interrupts:58 items:59 - description: combined legacy interrupt60 required:61 - "#address-cells"62 - "#interrupt-cells"63 - interrupt-controller64 - interrupts65 66 msi-map: true67 68 ranges:69 minItems: 270 maxItems: 371 72 vpcie3v3-supply: true73 74required:75 - msi-map76 77unevaluatedProperties: false78 79examples:80 - |81 #include <dt-bindings/interrupt-controller/arm-gic.h>82 83 bus {84 #address-cells = <2>;85 #size-cells = <2>;86 87 pcie3x2: pcie@fe280000 {88 compatible = "rockchip,rk3568-pcie";89 reg = <0x3 0xc0800000 0x0 0x390000>,90 <0x0 0xfe280000 0x0 0x10000>,91 <0x3 0x80000000 0x0 0x100000>;92 reg-names = "dbi", "apb", "config";93 bus-range = <0x20 0x2f>;94 clocks = <&cru 143>, <&cru 144>,95 <&cru 145>, <&cru 146>,96 <&cru 147>;97 clock-names = "aclk_mst", "aclk_slv",98 "aclk_dbi", "pclk",99 "aux";100 device_type = "pci";101 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,102 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,103 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,104 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,105 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;106 interrupt-names = "sys", "pmc", "msg", "legacy", "err";107 linux,pci-domain = <2>;108 max-link-speed = <2>;109 msi-map = <0x2000 &its 0x2000 0x1000>;110 num-lanes = <2>;111 phys = <&pcie30phy>;112 phy-names = "pcie-phy";113 power-domains = <&power 15>;114 ranges = <0x81000000 0x0 0x80800000 0x3 0x80800000 0x0 0x100000>,115 <0x83000000 0x0 0x80900000 0x3 0x80900000 0x0 0x3f700000>;116 resets = <&cru 193>;117 reset-names = "pipe";118 #address-cells = <3>;119 #size-cells = <2>;120 121 legacy-interrupt-controller {122 interrupt-controller;123 #address-cells = <0>;124 #interrupt-cells = <1>;125 interrupt-parent = <&gic>;126 interrupts = <GIC_SPI 72 IRQ_TYPE_EDGE_RISING>;127 };128 };129 };130...131