267 lines · yaml
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/pci/snps,dw-pcie-common.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Synopsys DWC PCIe RP/EP controller8 9maintainers:10 - Jingoo Han <jingoohan1@gmail.com>11 - Gustavo Pimentel <gustavo.pimentel@synopsys.com>12 13description:14 Generic Synopsys DesignWare PCIe Root Port and Endpoint controller15 properties.16 17select: false18 19properties:20 reg:21 description:22 DWC PCIe CSR space is normally accessed over the dedicated Data Bus23 Interface - DBI. In accordance with the reference manual the register24 configuration space belongs to the Configuration-Dependent Module (CDM)25 and is split up into several sub-parts Standard PCIe configuration26 space, Port Logic Registers (PL), Shadow Config-space Registers,27 iATU/eDMA registers. The particular sub-space is selected by the28 CDM/ELBI (dbi_cs) and CS2 (dbi_cs2) signals (selector bits). Such29 configuration provides a flexible interface for the system engineers to30 either map the particular space at a desired MMIO address or just leave31 them in a contiguous memory space if pure Native or AXI Bridge DBI access32 is selected. Note the PCIe CFG-space, PL and Shadow registers are33 specific for each activated function, while the rest of the sub-spaces34 are common for all of them (if there are more than one).35 minItems: 236 maxItems: 737 38 reg-names:39 minItems: 240 maxItems: 741 42 interrupts:43 description:44 There are two main sub-blocks which are normally capable of45 generating interrupts. It's System Information Interface and MSI46 interface. While the former one has some common for the Host and47 Endpoint controllers IRQ-signals, the later interface is obviously48 Root Complex specific since it's responsible for the incoming MSI49 messages signalling. The System Information IRQ signals are mainly50 responsible for reporting the generic PCIe hierarchy and Root51 Complex events like VPD IO request, general AER, PME, Hot-plug, link52 bandwidth change, link equalization request, INTx asserted/deasserted53 Message detection, embedded DMA Tx/Rx/Error.54 minItems: 155 maxItems: 2656 57 interrupt-names:58 minItems: 159 maxItems: 2660 61 clocks:62 description:63 DWC PCIe reference manual explicitly defines a set of the clocks required64 to get the controller working correctly. In general all of them can65 be divided into two groups':' application and core clocks. Note the66 platforms may have some of the clock sources unspecified in case if the67 corresponding domains are fed up from a common clock source.68 minItems: 169 maxItems: 770 71 clock-names:72 minItems: 173 maxItems: 774 items:75 oneOf:76 - description:77 Data Bus Interface (DBI) clock. Clock signal for the AXI-bus78 interface of the Configuration-Dependent Module, which is79 basically the set of the controller CSRs.80 const: dbi81 - description:82 Application AXI-bus Master interface clock. Basically this is83 a clock for the controller DMA interface (PCI-to-CPU).84 const: mstr85 - description:86 Application AXI-bus Slave interface clock. This is a clock for87 the CPU-to-PCI memory IO interface.88 const: slv89 - description:90 Controller Core-PCS PIPE interface clock. It's normally91 supplied by an external PCS-PHY.92 const: pipe93 - description:94 Controller Primary clock. It's assumed that all controller input95 signals (except resets) are synchronous to this clock.96 const: core97 - description:98 Auxiliary clock for the controller PMC domain. The controller99 partitioning implies having some parts to operate with this100 clock in some power management states.101 const: aux102 - description:103 Generic reference clock. In case if there are several104 interfaces fed up with a common clock source it's advisable to105 define it with this name (for instance pipe, core and aux can106 be connected to a single source of the periodic signal).107 const: ref108 - description:109 Clock for the PHY registers interface. Originally this is110 a PHY-viewport-based interface, but some platform may have111 specifically designed one.112 const: phy_reg113 - description:114 Vendor-specific clock names. Consider using the generic names115 above for new bindings.116 oneOf:117 - description: See native 'dbi' clock for details118 enum: [ pcie, pcie_apb_sys, aclk_dbi ]119 - description: See native 'mstr/slv' clock for details120 enum: [ pcie_bus, pcie_inbound_axi, pcie_aclk, aclk_mst, aclk_slv ]121 - description: See native 'pipe' clock for details122 enum: [ pcie_phy, pcie_phy_ref, link ]123 - description: See native 'aux' clock for details124 enum: [ pcie_aux ]125 - description: See native 'ref' clock for details.126 enum: [ gio ]127 - description: See nativs 'phy_reg' clock for details128 enum: [ pcie_apb_phy, pclk ]129 130 resets:131 description:132 DWC PCIe reference manual explicitly defines a set of the reset133 signals required to be de-asserted to properly activate the controller134 sub-parts. All of these signals can be divided into two sub-groups':'135 application and core resets with respect to the main sub-domains they136 are supposed to reset. Note the platforms may have some of these signals137 unspecified in case if they are automatically handled or aggregated into138 a comprehensive control module.139 minItems: 1140 maxItems: 10141 142 reset-names:143 minItems: 1144 maxItems: 10145 items:146 oneOf:147 - description: Data Bus Interface (DBI) domain reset148 const: dbi149 - description: AXI-bus Master interface reset150 const: mstr151 - description: AXI-bus Slave interface reset152 const: slv153 - description: Application-dependent interface reset154 const: app155 - description: Controller Non-sticky CSR flags reset156 const: non-sticky157 - description: Controller sticky CSR flags reset158 const: sticky159 - description: PIPE-interface (Core-PCS) logic reset160 const: pipe161 - description:162 Controller primary reset (resets everything except PMC module)163 const: core164 - description: PCS/PHY block reset165 const: phy166 - description: PMC hot reset signal167 const: hot168 - description: Cold reset signal169 const: pwr170 - description:171 Vendor-specific reset names. Consider using the generic names172 above for new bindings.173 oneOf:174 - description: See native 'app' reset for details175 enum: [ apps, gio, apb ]176 - description: See native 'phy' reset for details177 enum: [ pciephy, link ]178 - description: See native 'pwr' reset for details179 enum: [ turnoff ]180 181 phys:182 description:183 There can be up to the number of possible lanes PHYs specified placed in184 the phandle array in the line-based order. Obviously each the specified185 PHYs are supposed to be able to work in the PCIe mode with a speed186 implied by the DWC PCIe controller they are attached to.187 minItems: 1188 maxItems: 16189 190 phy-names:191 minItems: 1192 maxItems: 16193 oneOf:194 - description: Generic PHY names195 items:196 pattern: '^pcie[0-9]+$'197 - description:198 Vendor-specific PHY names. Consider using the generic199 names above for new bindings.200 items:201 oneOf:202 - pattern: '^pcie(-?phy[0-9]*)?$'203 - pattern: '^p2u-[0-7]$'204 205 reset-gpio:206 deprecated: true207 description:208 Reference to the GPIO-controlled PERST# signal. It is used to reset all209 the peripheral devices available on the PCIe bus.210 maxItems: 1211 212 reset-gpios:213 description:214 Reference to the GPIO-controlled PERST# signal. It is used to reset all215 the peripheral devices available on the PCIe bus.216 maxItems: 1217 218 max-link-speed:219 maximum: 5220 221 num-lanes:222 description:223 Number of PCIe link lanes to use. Can be omitted if the already brought224 up link is supposed to be preserved.225 maximum: 16226 227 num-ob-windows:228 $ref: /schemas/types.yaml#/definitions/uint32229 deprecated: true230 description:231 Number of outbound address translation windows. This parameter can be232 auto-detected based on the iATU memory writability. So there is no233 point in having a dedicated DT-property for it.234 maximum: 256235 236 num-ib-windows:237 $ref: /schemas/types.yaml#/definitions/uint32238 deprecated: true239 description:240 Number of inbound address translation windows. In the same way as241 for the outbound AT windows, this parameter can be auto-detected based242 on the iATU memory writability. There is no point having a dedicated243 DT-property for it either.244 maximum: 256245 246 num-viewport:247 $ref: /schemas/types.yaml#/definitions/uint32248 deprecated: true249 description:250 Number of outbound view ports configured in hardware. It's the same as251 the number of outbound AT windows.252 maximum: 256253 254 snps,enable-cdm-check:255 $ref: /schemas/types.yaml#/definitions/flag256 description:257 Enable automatic checking of CDM (Configuration Dependent Module)258 registers for data corruption. CDM registers include standard PCIe259 configuration space registers, Port Logic registers, DMA and iATU260 registers. This feature has been available since DWC PCIe v4.80a.261 262 dma-coherent: true263 264additionalProperties: true265 266...267