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1# SPDX-License-Identifier: GPL-2.02%YAML 1.23---4$id: http://devicetree.org/schemas/pci/snps,dw-pcie-ep.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Synopsys DesignWare PCIe endpoint interface8 9maintainers:10 - Jingoo Han <jingoohan1@gmail.com>11 - Gustavo Pimentel <gustavo.pimentel@synopsys.com>12 13description: |14 Synopsys DesignWare PCIe host controller endpoint15 16# Please create a separate DT-schema for your DWC PCIe Endpoint controller17# and make sure it's assigned with the vendor-specific compatible string.18select:19 properties:20 compatible:21 const: snps,dw-pcie-ep22 required:23 - compatible24 25allOf:26 - $ref: /schemas/pci/pci-ep.yaml#27 - $ref: /schemas/pci/snps,dw-pcie-common.yaml#28 29properties:30 reg:31 description:32 DBI, DBI2 reg-spaces and outbound memory window are required for the33 normal controller functioning. iATU memory IO region is also required34 if the space is unrolled (IP-core version >= 4.80a).35 minItems: 236 maxItems: 737 38 reg-names:39 minItems: 240 maxItems: 741 items:42 oneOf:43 - description:44 Basic DWC PCIe controller configuration-space accessible over45 the DBI interface. This memory space is either activated with46 CDM/ELBI = 0 and CS2 = 0 or is a contiguous memory region47 with all spaces. Note iATU/eDMA CSRs are indirectly accessible48 via the PL viewports on the DWC PCIe controllers older than49 v4.80a.50 const: dbi51 - description:52 Shadow DWC PCIe config-space registers. This space is selected53 by setting CDM/ELBI = 0 and CS2 = 1. This is an intermix of54 the PCI-SIG PCIe CFG-space with the shadow registers for some55 PCI Header space, PCI Standard and Extended Structures. It's56 mainly relevant for the end-point controller configuration,57 but still there are some shadow registers available for the58 Root Port mode too.59 const: dbi260 - description:61 External Local Bus registers. It's an application-dependent62 registers normally defined by the platform engineers. The space63 can be selected by setting CDM/ELBI = 1 and CS2 = 0 wires or can64 be accessed over some platform-specific means (for instance65 as a part of a system controller).66 enum: [ elbi, app ]67 - description:68 iATU/eDMA registers common for all device functions. It's an69 unrolled memory space with the internal Address Translation70 Unit and Enhanced DMA, which is selected by setting CDM/ELBI = 171 and CS2 = 1. For IP-core releases prior v4.80a, these registers72 have been programmed via an indirect addressing scheme using a73 set of viewport CSRs mapped into the PL space. Note iATU is74 normally mapped to the 0x0 address of this region, while eDMA75 is available at 0x80000 base address.76 const: atu77 - description:78 Platform-specific eDMA registers. Some platforms may have eDMA79 CSRs mapped in a non-standard base address. The registers offset80 can be changed or the MS/LS-bits of the address can be attached81 in an additional RTL block before the MEM-IO transactions reach82 the DW PCIe slave interface.83 const: dma84 - description:85 PHY/PCS configuration registers. Some platforms can have the86 PCS and PHY CSRs accessible over a dedicated memory mapped87 region, but mainly these registers are indirectly accessible88 either by means of the embedded PHY viewport schema or by some89 platform-specific method.90 const: phy91 - description:92 Outbound iATU-capable memory-region which will be used to93 generate various application-specific traffic on the PCIe bus94 hierarchy. It's usage scenario depends on the endpoint95 functionality, for instance it can be used to create MSI(X)96 messages.97 const: addr_space98 - description:99 Vendor-specific CSR names. Consider using the generic names above100 for new bindings.101 oneOf:102 - description: See native 'elbi/app' CSR region for details.103 enum: [ apb, link, appl ]104 - description: See native 'atu' CSR region for details.105 enum: [ atu_dma ]106 allOf:107 - contains:108 const: dbi109 - contains:110 const: addr_space111 112 interrupts:113 description:114 There is no mandatory IRQ signals for the normal controller functioning,115 but in addition to the native set the platforms may have a link- or116 PM-related IRQs specified.117 minItems: 1118 maxItems: 20119 120 interrupt-names:121 minItems: 1122 maxItems: 20123 items:124 oneOf:125 - description:126 Controller request to read or write virtual product data127 from/to the VPD capability registers.128 const: vpd129 - description:130 Link Equalization Request flag is set in the Link Status 2131 register (applicable if the corresponding IRQ is enabled in132 the Link Control 3 register).133 const: l_eq134 - description:135 Indicates that the eDMA Tx/Rx transfer is complete or that an136 error has occurred on the corresponding channel. eDMA can have137 eight Tx (Write) and Rx (Read) eDMA channels thus supporting up138 to 16 IRQ signals all together. Write eDMA channels shall go139 first in the ordered row as per default edma_int[*] bus setup.140 pattern: '^dma([0-9]|1[0-5])?$'141 - description:142 PCIe protocol correctable error or a Data Path protection143 correctable error is detected by the automotive/safety144 feature.145 const: sft_ce146 - description:147 Indicates that the internal safety mechanism has detected an148 uncorrectable error.149 const: sft_ue150 - description:151 Application-specific IRQ raised depending on the vendor-specific152 events basis.153 const: app154 - description:155 Interrupts triggered when the controller itself (in Endpoint mode)156 has sent an Assert_INT{A,B,C,D}/Desassert_INT{A,B,C,D} message to157 the upstream device.158 pattern: "^tx_int(a|b|c|d)$"159 - description:160 Combined interrupt signal raised when the controller has sent an161 Assert_INT{A,B,C,D} message. See "^tx_int(a|b|c|d)$" for details.162 const: legacy163 - description:164 Vendor-specific IRQ names. Consider using the generic names above165 for new bindings.166 oneOf:167 - description: See native "app" IRQ for details168 enum: [ intr, sys, pmc, msg, err ]169 170 max-functions:171 maximum: 32172 173required:174 - compatible175 - reg176 - reg-names177 178additionalProperties: true179 180examples:181 - |182 pcie-ep@dfd00000 {183 compatible = "snps,dw-pcie-ep";184 reg = <0xdfc00000 0x0001000>, /* IP registers 1 */185 <0xdfc01000 0x0001000>, /* IP registers 2 */186 <0xd0000000 0x2000000>; /* Configuration space */187 reg-names = "dbi", "dbi2", "addr_space";188 189 interrupts = <23>, <24>;190 interrupt-names = "dma0", "dma1";191 192 clocks = <&sys_clk 12>, <&sys_clk 24>;193 clock-names = "dbi", "ref";194 195 resets = <&sys_rst 12>, <&sys_rst 24>;196 reset-names = "dbi", "phy";197 198 phys = <&pcie_phy0>, <&pcie_phy1>, <&pcie_phy2>, <&pcie_phy3>;199 phy-names = "pcie0", "pcie1", "pcie2", "pcie3";200 201 max-link-speed = <3>;202 max-functions = /bits/ 8 <4>;203 };204