135 lines · yaml
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/pci/socionext,uniphier-pcie-ep.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Socionext UniPhier PCIe endpoint controller8 9description: |10 UniPhier PCIe endpoint controller is based on the Synopsys DesignWare11 PCI core. It shares common features with the PCIe DesignWare core and12 inherits common properties defined in13 Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml.14 15maintainers:16 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>17 18properties:19 compatible:20 enum:21 - socionext,uniphier-pro5-pcie-ep22 - socionext,uniphier-nx1-pcie-ep23 24 reg:25 minItems: 426 maxItems: 527 28 reg-names:29 minItems: 430 items:31 - const: dbi32 - const: dbi233 - const: link34 - const: addr_space35 - const: atu36 37 clocks:38 minItems: 139 maxItems: 240 41 clock-names:42 minItems: 143 maxItems: 244 45 resets:46 minItems: 147 maxItems: 248 49 reset-names:50 minItems: 151 maxItems: 252 53 num-ib-windows:54 const: 1655 56 num-ob-windows:57 const: 1658 59 num-lanes: true60 61 phys:62 maxItems: 163 64 phy-names:65 const: pcie-phy66 67allOf:68 - $ref: /schemas/pci/snps,dw-pcie-ep.yaml#69 - if:70 properties:71 compatible:72 contains:73 const: socionext,uniphier-pro5-pcie-ep74 then:75 properties:76 reg:77 maxItems: 478 reg-names:79 maxItems: 480 clocks:81 minItems: 282 clock-names:83 items:84 - const: gio85 - const: link86 resets:87 minItems: 288 reset-names:89 items:90 - const: gio91 - const: link92 else:93 properties:94 reg:95 minItems: 596 reg-names:97 minItems: 598 clocks:99 maxItems: 1100 clock-names:101 const: link102 resets:103 maxItems: 1104 reset-names:105 const: link106 107required:108 - compatible109 - reg110 - reg-names111 - clocks112 - clock-names113 - resets114 - reset-names115 116unevaluatedProperties: false117 118examples:119 - |120 pcie_ep: pcie-ep@66000000 {121 compatible = "socionext,uniphier-pro5-pcie-ep";122 reg-names = "dbi", "dbi2", "link", "addr_space";123 reg = <0x66000000 0x1000>, <0x66001000 0x1000>,124 <0x66010000 0x10000>, <0x67000000 0x400000>;125 clock-names = "gio", "link";126 clocks = <&sys_clk 12>, <&sys_clk 24>;127 reset-names = "gio", "link";128 resets = <&sys_rst 12>, <&sys_rst 24>;129 num-ib-windows = <16>;130 num-ob-windows = <16>;131 num-lanes = <4>;132 phy-names = "pcie-phy";133 phys = <&pcie_phy>;134 };135