118 lines · yaml
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/pci/socionext,uniphier-pcie.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Socionext UniPhier PCIe host controller8 9description: |10 UniPhier PCIe host controller is based on the Synopsys DesignWare11 PCI core. It shares common features with the PCIe DesignWare core and12 inherits common properties defined in13 Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml.14 15maintainers:16 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>17 18allOf:19 - $ref: /schemas/pci/snps,dw-pcie.yaml#20 21properties:22 compatible:23 enum:24 - socionext,uniphier-pcie25 26 reg:27 minItems: 328 maxItems: 429 30 reg-names:31 minItems: 332 items:33 - const: dbi34 - const: link35 - const: config36 - const: atu37 38 clocks:39 maxItems: 140 41 resets:42 maxItems: 143 44 num-viewport: true45 46 num-lanes: true47 48 phys:49 maxItems: 150 51 phy-names:52 const: pcie-phy53 54 interrupt-controller:55 type: object56 additionalProperties: false57 58 properties:59 interrupt-controller: true60 61 '#interrupt-cells':62 const: 163 64 interrupts:65 maxItems: 166 67required:68 - compatible69 - reg70 - reg-names71 - clocks72 - resets73 74unevaluatedProperties: false75 76examples:77 - |78 bus {79 gic: interrupt-controller {80 interrupt-controller;81 #interrupt-cells = <3>;82 };83 };84 85 pcie: pcie@66000000 {86 compatible = "socionext,uniphier-pcie";87 reg-names = "dbi", "link", "config";88 reg = <0x66000000 0x1000>, <0x66010000 0x10000>, <0x2fff0000 0x10000>;89 #address-cells = <3>;90 #size-cells = <2>;91 clocks = <&sys_clk 24>;92 resets = <&sys_rst 24>;93 num-lanes = <1>;94 num-viewport = <1>;95 bus-range = <0x0 0xff>;96 device_type = "pci";97 ranges = <0x81000000 0 0x00000000 0x2ffe0000 0 0x00010000>,98 <0x82000000 0 0x00000000 0x20000000 0 0x0ffe0000>;99 phy-names = "pcie-phy";100 phys = <&pcie_phy>;101 #interrupt-cells = <1>;102 interrupt-names = "dma", "msi";103 interrupt-parent = <&gic>;104 interrupts = <0 224 4>, <0 225 4>;105 interrupt-map-mask = <0 0 0 7>;106 interrupt-map = <0 0 0 1 &pcie_intc 0>,107 <0 0 0 2 &pcie_intc 1>,108 <0 0 0 3 &pcie_intc 2>,109 <0 0 0 4 &pcie_intc 3>;110 111 pcie_intc: interrupt-controller {112 interrupt-controller;113 #interrupt-cells = <1>;114 interrupt-parent = <&gic>;115 interrupts = <0 226 4>;116 };117 };118