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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2# Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/3%YAML 1.24---5$id: http://devicetree.org/schemas/pci/ti,j721e-pci-ep.yaml#6$schema: http://devicetree.org/meta-schemas/core.yaml#7 8title: TI J721E PCI EP (PCIe Wrapper)9 10maintainers:11 - Kishon Vijay Abraham I <kishon@ti.com>12 13properties:14 compatible:15 oneOf:16 - const: ti,j721e-pcie-ep17 - const: ti,j784s4-pcie-ep18 - description: PCIe EP controller in AM6419 items:20 - const: ti,am64-pcie-ep21 - const: ti,j721e-pcie-ep22 - description: PCIe EP controller in J720023 items:24 - const: ti,j7200-pcie-ep25 - const: ti,j721e-pcie-ep26 27 reg:28 maxItems: 429 30 reg-names:31 items:32 - const: intd_cfg33 - const: user_cfg34 - const: reg35 - const: mem36 37 ti,syscon-pcie-ctrl:38 $ref: /schemas/types.yaml#/definitions/phandle-array39 items:40 - items:41 - description: Phandle to the SYSCON entry42 - description: pcie_ctrl register offset within SYSCON43 description: Specifier for configuring PCIe mode and link speed.44 45 power-domains:46 maxItems: 147 48 clocks:49 maxItems: 150 description: clock-specifier to represent input to the PCIe51 52 clock-names:53 items:54 - const: fck55 56 dma-coherent:57 description: Indicates that the PCIe IP block can ensure the coherency58 59 interrupts:60 maxItems: 161 62 interrupt-names:63 items:64 - const: link_state65 66allOf:67 - $ref: cdns-pcie-ep.yaml#68 - if:69 properties:70 compatible:71 enum:72 - ti,am64-pcie-ep73 then:74 properties:75 num-lanes:76 const: 177 78 - if:79 properties:80 compatible:81 enum:82 - ti,j7200-pcie-ep83 - ti,j721e-pcie-ep84 then:85 properties:86 num-lanes:87 minimum: 188 maximum: 289 90 - if:91 properties:92 compatible:93 enum:94 - ti,j784s4-pcie-ep95 then:96 properties:97 num-lanes:98 minimum: 199 maximum: 4100 101required:102 - compatible103 - reg104 - reg-names105 - ti,syscon-pcie-ctrl106 - max-link-speed107 - num-lanes108 - power-domains109 - clocks110 - clock-names111 - max-functions112 - phys113 - phy-names114 115unevaluatedProperties: false116 117examples:118 - |119 #include <dt-bindings/soc/ti,sci_pm_domain.h>120 121 bus {122 #address-cells = <2>;123 #size-cells = <2>;124 125 pcie0_ep: pcie-ep@d000000 {126 compatible = "ti,j721e-pcie-ep";127 reg = <0x00 0x02900000 0x00 0x1000>,128 <0x00 0x02907000 0x00 0x400>,129 <0x00 0x0d000000 0x00 0x00800000>,130 <0x00 0x10000000 0x00 0x08000000>;131 reg-names = "intd_cfg", "user_cfg", "reg", "mem";132 ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x4070>;133 max-link-speed = <3>;134 num-lanes = <2>;135 power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>;136 clocks = <&k3_clks 239 1>;137 clock-names = "fck";138 max-functions = /bits/ 8 <6>;139 dma-coherent;140 phys = <&serdes0_pcie_link>;141 phy-names = "pcie-phy";142 };143 };144