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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2# Copyright 2021 Arm Ltd.3%YAML 1.24---5$id: http://devicetree.org/schemas/perf/arm,dsu-pmu.yaml#6$schema: http://devicetree.org/meta-schemas/core.yaml#7 8title: ARM DynamIQ Shared Unit (DSU) Performance Monitor Unit (PMU)9 10maintainers:11 - Suzuki K Poulose <suzuki.poulose@arm.com>12 - Robin Murphy <robin.murphy@arm.com>13 14description:15 ARM DynamIQ Shared Unit (DSU) integrates one or more CPU cores with a shared16 L3 memory system, control logic and external interfaces to form a multicore17 cluster. The PMU enables gathering various statistics on the operation of the18 DSU. The PMU provides independent 32-bit counters that can count any of the19 supported events, along with a 64-bit cycle counter. The PMU is accessed via20 CPU system registers and has no MMIO component.21 22properties:23 compatible:24 oneOf:25 - const: arm,dsu-pmu26 - items:27 - const: arm,dsu-110-pmu28 - const: arm,dsu-pmu29 30 interrupts:31 items:32 - description: nCLUSTERPMUIRQ interrupt33 34 cpus:35 minItems: 136 maxItems: 1237 description: List of phandles for the CPUs connected to this DSU instance.38 39required:40 - compatible41 - interrupts42 - cpus43 44additionalProperties: false45