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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/perf/marvell-cn10k-tad.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Marvell CN10K LLC-TAD performance monitor8 9maintainers:10 - Bhaskara Budiredla <bbudiredla@marvell.com>11 12description: |13 The Tag-and-Data units (TADs) maintain coherence and contain CN10K14 shared on-chip last level cache (LLC). The tad pmu measures the15 performance of last-level cache. Each tad pmu supports up to eight16 counters.17 18 The DT setup comprises of number of tad blocks, the sizes of pmu19 regions, tad blocks and overall base address of the HW.20 21properties:22 compatible:23 const: marvell,cn10k-tad-pmu24 25 reg:26 maxItems: 127 28 marvell,tad-cnt:29 description: specifies the number of tads on the soc30 $ref: /schemas/types.yaml#/definitions/uint3231 32 marvell,tad-page-size:33 description: specifies the size of each tad page34 $ref: /schemas/types.yaml#/definitions/uint3235 36 marvell,tad-pmu-page-size:37 description: specifies the size of page that the pmu uses38 $ref: /schemas/types.yaml#/definitions/uint3239 40required:41 - compatible42 - reg43 - marvell,tad-cnt44 - marvell,tad-page-size45 - marvell,tad-pmu-page-size46 47additionalProperties: false48 49examples:50 - |51 52 tad {53 #address-cells = <2>;54 #size-cells = <2>;55 56 tad_pmu@80000000 {57 compatible = "marvell,cn10k-tad-pmu";58 reg = <0x87e2 0x80000000 0x0 0x1000>;59 marvell,tad-cnt = <1>;60 marvell,tad-page-size = <0x1000>;61 marvell,tad-pmu-page-size = <0x1000>;62 };63 };64