brintos / linux-shallow public Read only

1# SPDX-License-Identifier: GPL-2.02%YAML 1.23---4$id: http://devicetree.org/schemas/phy/allwinner,sun50i-h6-usb-phy.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Allwinner H6 USB PHY8 9maintainers:10  - Chen-Yu Tsai <wens@csie.org>11  - Maxime Ripard <mripard@kernel.org>12 13properties:14  "#phy-cells":15    const: 116 17  compatible:18    const: allwinner,sun50i-h6-usb-phy19 20  reg:21    items:22      - description: PHY Control registers23      - description: PHY PMU0 registers24      - description: PHY PMU3 registers25 26  reg-names:27    items:28      - const: phy_ctrl29      - const: pmu030      - const: pmu331 32  clocks:33    items:34      - description: USB OTG PHY bus clock35      - description: USB Host PHY bus clock36 37  clock-names:38    items:39      - const: usb0_phy40      - const: usb3_phy41 42  resets:43    items:44      - description: USB OTG reset45      - description: USB Host Controller reset46 47  reset-names:48    items:49      - const: usb0_reset50      - const: usb3_reset51 52  usb0_id_det-gpios:53    maxItems: 154    description: GPIO to the USB OTG ID pin55 56  usb0_vbus_det-gpios:57    maxItems: 158    description: GPIO to the USB OTG VBUS detect pin59 60  usb0_vbus_power-supply:61    description: Power supply to detect the USB OTG VBUS62 63  usb0_vbus-supply:64    description: Regulator controlling USB OTG VBUS65 66  usb3_vbus-supply:67    description: Regulator controlling USB3 Host controller68 69required:70  - "#phy-cells"71  - compatible72  - clocks73  - clock-names74  - reg75  - reg-names76  - resets77  - reset-names78 79additionalProperties: false80 81examples:82  - |83    #include <dt-bindings/gpio/gpio.h>84    #include <dt-bindings/clock/sun50i-h6-ccu.h>85    #include <dt-bindings/reset/sun50i-h6-ccu.h>86 87    phy@5100400 {88        #phy-cells = <1>;89        compatible = "allwinner,sun50i-h6-usb-phy";90        reg = <0x05100400 0x24>,91              <0x05101800 0x4>,92              <0x05311800 0x4>;93        reg-names = "phy_ctrl",94                    "pmu0",95                    "pmu3";96        clocks = <&ccu CLK_USB_PHY0>,97                 <&ccu CLK_USB_PHY3>;98        clock-names = "usb0_phy",99                      "usb3_phy";100        resets = <&ccu RST_USB_PHY0>,101                 <&ccu RST_USB_PHY3>;102        reset-names = "usb0_reset",103                      "usb3_reset";104        usb0_id_det-gpios = <&pio 2 6 GPIO_ACTIVE_HIGH>; /* PC6 */105        usb0_vbus-supply = <&reg_vcc5v>;106        usb3_vbus-supply = <&reg_vcc5v>;107    };108