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1# SPDX-License-Identifier: GPL-2.02%YAML 1.23---4$id: http://devicetree.org/schemas/phy/allwinner,sun6i-a31-mipi-dphy.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Allwinner A31 MIPI D-PHY Controller8 9maintainers:10 - Chen-Yu Tsai <wens@csie.org>11 - Maxime Ripard <mripard@kernel.org>12 13properties:14 "#phy-cells":15 const: 016 17 compatible:18 oneOf:19 - const: allwinner,sun6i-a31-mipi-dphy20 - const: allwinner,sun50i-a100-mipi-dphy21 - items:22 - const: allwinner,sun50i-a64-mipi-dphy23 - const: allwinner,sun6i-a31-mipi-dphy24 - items:25 - const: allwinner,sun20i-d1-mipi-dphy26 - const: allwinner,sun50i-a100-mipi-dphy27 28 reg:29 maxItems: 130 31 interrupts:32 maxItems: 133 34 clocks:35 items:36 - description: Bus Clock37 - description: Module Clock38 39 clock-names:40 items:41 - const: bus42 - const: mod43 44 resets:45 maxItems: 146 47 allwinner,direction:48 $ref: /schemas/types.yaml#/definitions/string49 description: |50 Direction of the D-PHY:51 - "rx" for receiving (e.g. when used with MIPI CSI-2);52 - "tx" for transmitting (e.g. when used with MIPI DSI).53 54 enum:55 - tx56 - rx57 default: tx58 59required:60 - "#phy-cells"61 - compatible62 - reg63 - interrupts64 - clocks65 - clock-names66 - resets67 68additionalProperties: false69 70examples:71 - |72 #include <dt-bindings/interrupt-controller/arm-gic.h>73 74 dphy0: d-phy@1ca1000 {75 compatible = "allwinner,sun6i-a31-mipi-dphy";76 reg = <0x01ca1000 0x1000>;77 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;78 clocks = <&ccu 23>, <&ccu 97>;79 clock-names = "bus", "mod";80 resets = <&ccu 4>;81 #phy-cells = <0>;82 };83 84...85