brintos / linux-shallow public Read only

1# SPDX-License-Identifier: GPL-2.02%YAML 1.23---4$id: http://devicetree.org/schemas/phy/allwinner,sun8i-a23-usb-phy.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Allwinner A23 USB PHY8 9maintainers:10  - Chen-Yu Tsai <wens@csie.org>11  - Maxime Ripard <mripard@kernel.org>12 13properties:14  "#phy-cells":15    const: 116 17  compatible:18    enum:19      - allwinner,sun8i-a23-usb-phy20      - allwinner,sun8i-a33-usb-phy21 22  reg:23    items:24      - description: PHY Control registers25      - description: PHY PMU1 registers26 27  reg-names:28    items:29      - const: phy_ctrl30      - const: pmu131 32  clocks:33    items:34      - description: USB OTG PHY bus clock35      - description: USB Host 0 PHY bus clock36 37  clock-names:38    items:39      - const: usb0_phy40      - const: usb1_phy41 42  resets:43    items:44      - description: USB OTG reset45      - description: USB Host 1 Controller reset46 47  reset-names:48    items:49      - const: usb0_reset50      - const: usb1_reset51 52  usb0_id_det-gpios:53    maxItems: 154    description: GPIO to the USB OTG ID pin55 56  usb0_vbus_det-gpios:57    maxItems: 158    description: GPIO to the USB OTG VBUS detect pin59 60  usb0_vbus_power-supply:61    description: Power supply to detect the USB OTG VBUS62 63  usb0_vbus-supply:64    description: Regulator controlling USB OTG VBUS65 66  usb1_vbus-supply:67    description: Regulator controlling USB1 Host controller68 69required:70  - "#phy-cells"71  - compatible72  - clocks73  - clock-names74  - reg75  - reg-names76  - resets77  - reset-names78 79additionalProperties: false80 81examples:82  - |83    #include <dt-bindings/gpio/gpio.h>84    #include <dt-bindings/clock/sun8i-a23-a33-ccu.h>85    #include <dt-bindings/reset/sun8i-a23-a33-ccu.h>86 87    phy@1c19400 {88        #phy-cells = <1>;89        compatible = "allwinner,sun8i-a23-usb-phy";90        reg = <0x01c19400 0x10>, <0x01c1a800 0x4>;91        reg-names = "phy_ctrl", "pmu1";92        clocks = <&ccu CLK_USB_PHY0>,93                 <&ccu CLK_USB_PHY1>;94        clock-names = "usb0_phy",95                      "usb1_phy";96        resets = <&ccu RST_USB_PHY0>,97                 <&ccu RST_USB_PHY1>;98        reset-names = "usb0_reset",99                      "usb1_reset";100        usb0_id_det-gpios = <&pio 1 3 GPIO_ACTIVE_HIGH>; /* PB3 */101        usb0_vbus_power-supply = <&usb_power_supply>;102        usb0_vbus-supply = <&reg_drivevbus>;103        usb1_vbus-supply = <&reg_usb1_vbus>;104    };105