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1# SPDX-License-Identifier: GPL-2.02%YAML 1.23---4$id: http://devicetree.org/schemas/phy/allwinner,sun8i-a83t-usb-phy.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Allwinner A83t USB PHY8 9maintainers:10 - Chen-Yu Tsai <wens@csie.org>11 - Maxime Ripard <mripard@kernel.org>12 13properties:14 "#phy-cells":15 const: 116 17 compatible:18 const: allwinner,sun8i-a83t-usb-phy19 20 reg:21 items:22 - description: PHY Control registers23 - description: PHY PMU1 registers24 - description: PHY PMU2 registers25 26 reg-names:27 items:28 - const: phy_ctrl29 - const: pmu130 - const: pmu231 32 clocks:33 items:34 - description: USB OTG PHY bus clock35 - description: USB Host 0 PHY bus clock36 - description: USB Host 1 PHY bus clock37 - description: USB HSIC 12MHz clock38 39 clock-names:40 items:41 - const: usb0_phy42 - const: usb1_phy43 - const: usb2_phy44 - const: usb2_hsic_12M45 46 resets:47 items:48 - description: USB OTG reset49 - description: USB Host 1 Controller reset50 - description: USB Host 2 Controller reset51 52 reset-names:53 items:54 - const: usb0_reset55 - const: usb1_reset56 - const: usb2_reset57 58 usb0_id_det-gpios:59 maxItems: 160 description: GPIO to the USB OTG ID pin61 62 usb0_vbus_det-gpios:63 maxItems: 164 description: GPIO to the USB OTG VBUS detect pin65 66 usb0_vbus_power-supply:67 description: Power supply to detect the USB OTG VBUS68 69 usb0_vbus-supply:70 description: Regulator controlling USB OTG VBUS71 72 usb1_vbus-supply:73 description: Regulator controlling USB1 Host controller74 75 usb2_vbus-supply:76 description: Regulator controlling USB2 Host controller77 78required:79 - "#phy-cells"80 - compatible81 - clocks82 - clock-names83 - reg84 - reg-names85 - resets86 - reset-names87 88additionalProperties: false89 90examples:91 - |92 #include <dt-bindings/gpio/gpio.h>93 #include <dt-bindings/clock/sun8i-a83t-ccu.h>94 #include <dt-bindings/reset/sun8i-a83t-ccu.h>95 96 phy@1c19400 {97 #phy-cells = <1>;98 compatible = "allwinner,sun8i-a83t-usb-phy";99 reg = <0x01c19400 0x10>,100 <0x01c1a800 0x14>,101 <0x01c1b800 0x14>;102 reg-names = "phy_ctrl",103 "pmu1",104 "pmu2";105 clocks = <&ccu CLK_USB_PHY0>,106 <&ccu CLK_USB_PHY1>,107 <&ccu CLK_USB_HSIC>,108 <&ccu CLK_USB_HSIC_12M>;109 clock-names = "usb0_phy",110 "usb1_phy",111 "usb2_phy",112 "usb2_hsic_12M";113 resets = <&ccu RST_USB_PHY0>,114 <&ccu RST_USB_PHY1>,115 <&ccu RST_USB_HSIC>;116 reset-names = "usb0_reset",117 "usb1_reset",118 "usb2_reset";119 usb0_id_det-gpios = <&pio 7 11 GPIO_ACTIVE_HIGH>; /* PH11 */120 usb0_vbus_power-supply = <&usb_power_supply>;121 usb0_vbus-supply = <®_drivevbus>;122 usb1_vbus-supply = <®_usb1_vbus>;123 usb2_vbus-supply = <®_usb2_vbus>;124 };125