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1# SPDX-License-Identifier: GPL-2.02%YAML 1.23---4$id: http://devicetree.org/schemas/phy/allwinner,sun8i-v3s-usb-phy.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Allwinner V3s USB PHY8 9maintainers:10 - Chen-Yu Tsai <wens@csie.org>11 - Maxime Ripard <mripard@kernel.org>12 13properties:14 "#phy-cells":15 const: 116 17 compatible:18 const: allwinner,sun8i-v3s-usb-phy19 20 reg:21 items:22 - description: PHY Control registers23 - description: PHY PMU0 registers24 25 reg-names:26 items:27 - const: phy_ctrl28 - const: pmu029 30 clocks:31 maxItems: 132 description: USB OTG PHY bus clock33 34 clock-names:35 const: usb0_phy36 37 resets:38 maxItems: 139 description: USB OTG reset40 41 reset-names:42 const: usb0_reset43 44 usb0_id_det-gpios:45 maxItems: 146 description: GPIO to the USB OTG ID pin47 48 usb0_vbus_det-gpios:49 maxItems: 150 description: GPIO to the USB OTG VBUS detect pin51 52 usb0_vbus_power-supply:53 description: Power supply to detect the USB OTG VBUS54 55 usb0_vbus-supply:56 description: Regulator controlling USB OTG VBUS57 58required:59 - "#phy-cells"60 - compatible61 - clocks62 - clock-names63 - reg64 - reg-names65 - resets66 - reset-names67 68additionalProperties: false69 70examples:71 - |72 #include <dt-bindings/gpio/gpio.h>73 #include <dt-bindings/clock/sun8i-v3s-ccu.h>74 #include <dt-bindings/reset/sun8i-v3s-ccu.h>75 76 phy@1c19400 {77 #phy-cells = <1>;78 compatible = "allwinner,sun8i-v3s-usb-phy";79 reg = <0x01c19400 0x2c>,80 <0x01c1a800 0x4>;81 reg-names = "phy_ctrl",82 "pmu0";83 clocks = <&ccu CLK_USB_PHY0>;84 clock-names = "usb0_phy";85 resets = <&ccu RST_USB_PHY0>;86 reset-names = "usb0_reset";87 usb0_id_det-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>;88 };89