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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/phy/allwinner,suniv-f1c100s-usb-phy.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Allwinner F1C100s USB PHY8 9maintainers:10 - Chen-Yu Tsai <wens@csie.org>11 - Maxime Ripard <mripard@kernel.org>12 13properties:14 "#phy-cells":15 const: 116 17 compatible:18 const: allwinner,suniv-f1c100s-usb-phy19 20 reg:21 maxItems: 122 description: PHY Control registers23 24 reg-names:25 const: phy_ctrl26 27 clocks:28 maxItems: 129 description: USB OTG PHY bus clock30 31 clock-names:32 const: usb0_phy33 34 resets:35 maxItems: 136 description: USB OTG reset37 38 reset-names:39 const: usb0_reset40 41 usb0_id_det-gpios:42 maxItems: 143 description: GPIO to the USB OTG ID pin44 45 usb0_vbus_det-gpios:46 maxItems: 147 description: GPIO to the USB OTG VBUS detect pin48 49 usb0_vbus_power-supply:50 description: Power supply to detect the USB OTG VBUS51 52 usb0_vbus-supply:53 description: Regulator controlling USB OTG VBUS54 55required:56 - "#phy-cells"57 - compatible58 - clocks59 - clock-names60 - reg61 - reg-names62 - resets63 - reset-names64 65additionalProperties: false66 67examples:68 - |69 #include <dt-bindings/gpio/gpio.h>70 #include <dt-bindings/clock/suniv-ccu-f1c100s.h>71 #include <dt-bindings/reset/suniv-ccu-f1c100s.h>72 73 phy@1c13400 {74 compatible = "allwinner,suniv-f1c100s-usb-phy";75 reg = <0x01c13400 0x10>;76 reg-names = "phy_ctrl";77 clocks = <&ccu CLK_USB_PHY0>;78 clock-names = "usb0_phy";79 resets = <&ccu RST_USB_PHY0>;80 reset-names = "usb0_reset";81 #phy-cells = <1>;82 usb0_id_det-gpios = <&pio 4 2 GPIO_ACTIVE_HIGH>;83 };84